US-20260130208-A1 - INTEGRATED CIRCUIT STRUCTURE HAVING ANTI-FUSE STRUCTURE

Abstract

Integrated circuit structures having anti-fuse structures, and methods of fabricating integrated circuit structures having anti-fuse structures, are described. For example, an integrated circuit structure includes a first vertical stack of horizontal nanowires. A first gate structure is over the first vertical stack of horizontal nanowires, the first gate structure including a first gate dielectric and a first gate electrode completely surrounding a channel region of each nanowire of the first vertical stack of horizontal nanowires. The integrated circuit structure also includes a second vertical stack of horizontal nanowires. A second gate structure is over the second vertical stack of horizontal nanowires, the second gate structure including a second gate dielectric and a second gate electrode only partially surrounding a channel region of each nanowire of the second vertical stack of horizontal nanowires.

Inventors

• Changyok Park

Assignees

• INTEL CORPORATION

Dates

Publication Date

20260507

Application Date

20251229

Claims (20)

1. 1 . An integrated circuit structure, comprising: a vertical stack of horizontal nanowires; and a gate structure over the vertical stack of horizontal nanowires, the gate structure comprising a gate dielectric and a gate electrode only partially surrounding a channel region of each nanowire of the vertical stack of horizontal nanowires, wherein a semiconductor material is between neighboring ones of the nanowires of the vertical stack of horizontal nanowires, and wherein a portion of the gate dielectric and the gate electrode is laterally adjacent to the semiconductor material and is vertically between the neighboring ones of the nanowires of the vertical stack of horizontal nanowires.
2. 2 . The integrated circuit structure of claim 1 , wherein the semiconductor material comprises silicon and germanium, and the vertical stack of horizontal nanowires comprises silicon.
3. 3 . The integrated circuit structure of claim 1 , wherein the vertical stack of horizontal nanowires is over a sub-fin.
4. 4 . The integrated circuit structure of claim 1 , wherein vertical stack of horizontal nanowires is included in a GAA-based anti-fuse.
5. 5 . The integrated circuit structure of claim 1 , wherein the gate dielectric comprises a high-k dielectric layer, and the gate electrode comprises a metal.
6. 6 . A method of fabricating an integrated circuit structure, the method comprising: forming a vertical stack of horizontal nanowires; and forming a gate structure over the vertical stack of horizontal nanowires, the gate structure comprising a gate dielectric and a gate electrode only partially surrounding a channel region of each nanowire of the vertical stack of horizontal nanowires, wherein a semiconductor material is between neighboring ones of the nanowires of the vertical stack of horizontal nanowires, and wherein a portion of the gate dielectric and the gate electrode is laterally adjacent to the semiconductor material and is vertically between the neighboring ones of the nanowires of the vertical stack of horizontal nanowires.
7. 7 . The method of claim 6 , wherein the semiconductor material comprises silicon and germanium, and the vertical stack of horizontal nanowires comprises silicon.
8. 8 . The method of claim 6 , wherein the vertical stack of horizontal nanowires is over a sub-fin.
9. 9 . The method of claim 6 , wherein vertical stack of horizontal nanowires is included in a GAA-based anti-fuse.
10. 10 . The method of claim 6 , wherein the gate dielectric comprises a high-k dielectric layer, and the gate electrode comprises a metal.
11. 11 . A computing device, comprising: a board; and a component coupled to the board, the component including an integrated circuit structure, comprising: a vertical stack of horizontal nanowires; and a gate structure over the vertical stack of horizontal nanowires, the gate structure comprising a gate dielectric and a gate electrode only partially surrounding a channel region of each nanowire of the vertical stack of horizontal nanowires, wherein a semiconductor material is between neighboring ones of the nanowires of the vertical stack of horizontal nanowires, and wherein a portion of the gate dielectric and the gate electrode is laterally adjacent to the semiconductor material and is vertically between the neighboring ones of the nanowires of the vertical stack of horizontal nanowires.
12. 12 . The computing device of claim 11 , wherein the semiconductor material comprises silicon and germanium, and the vertical stack of horizontal nanowires comprises silicon.
13. 13 . The computing device of claim 11 , wherein vertical stack of horizontal nanowires is included in a GAA-based anti-fuse.
14. 14 . The computing device of claim 11 , further comprising: a memory coupled to the board.
15. 15 . The computing device of claim 11 , further comprising: a communication chip coupled to the board.
16. 16 . The computing device of claim 11 , further comprising: a battery coupled to the board.
17. 17 . The computing device of claim 11 , further comprising: a camera coupled to the board.
18. 18 . The computing device of claim 11 , further comprising: a display coupled to the board.
19. 19 . The computing device of claim 11 , wherein the component is a packaged integrated circuit die.
20. 20 . The computing device of claim 11 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of U.S. patent application Ser. No. 17/561,687, filed on Dec. 23, 2021, the entire contents of which is hereby incorporated by reference herein. TECHNICAL FIELD Embodiments of the disclosure are in the field of integrated circuit structures and processing and, in particular, integrated circuit structures having anti-fuse structures and methods of fabricating integrated circuit structures having anti-fuse structures. BACKGROUND For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant. In the manufacture of integrated circuit devices, multi-gate transistors, such as tri-gate transistors, have become more prevalent as device dimensions continue to scale down. In conventional processes, tri-gate transistors are generally fabricated on either bulk silicon substrates or silicon-on-insulator substrates. In some instances, bulk silicon substrates are preferred due to their lower cost and because they enable a less complicated tri-gate fabrication process. In another aspect, maintaining mobility improvement and short channel control as microelectronic device dimensions scale below the 10 nanometer (nm) node provides a challenge in device fabrication. Nanowires used to fabricate devices provide improved short channel control. Scaling multi-gate and nanowire transistors has not been without consequence, however. As the dimensions of these fundamental building blocks of microelectronic circuitry are reduced and as the sheer number of fundamental building blocks fabricated in a given region is increased, the constraints on the lithographic processes used to pattern these building blocks have become overwhelming. In particular, there may be a trade-off between the smallest dimension of a feature patterned in a semiconductor stack (the critical dimension) and the spacing between such features. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 and 2 illustrate cross-sectional views representing various operations in a method of fabricating an integrated circuit structure including an anti-fuse structure, in accordance with an embodiment of the present disclosure. FIGS. 3A and 3B illustrate cross-sectional views representing various operations in a method of fabricating an integrated circuit structure including an anti-fuse structure, in accordance with an embodiment of the present disclosure. FIGS. 4A and 4B illustrate cross-sectional views representing various operations in a method of fabricating an integrated circuit structure including an anti-fuse structure, in accordance with an embodiment of the present disclosure. FIGS. 5A and 5B illustrate cross-sectional views representing various operations in a method of fabricating an integrated circuit structure including an anti-fuse structure, in accordance with an embodiment of the present disclosure. FIG. 6 illustrates a cross-sectional view representing an integrated circuit structure including an anti-fuse structure, in accordance with an embodiment of the present disclosure. FIGS. 7A-7J illustrates cross-sectional views of various operations in a method of fabricating a gate-all-around integrated circuit structure, in accordance with an embodiment of the present disclosure. FIG. 8 illustrates a cross-sectional view of a non-planar integrated circuit structure as taken along a gate line, in accordance with an embodiment of the present disclosure. FIG. 9 illustrates cross-sectional views taken through nanowires and fins for a non-endcap architecture (left-hand side (a)) versus a self-aligned gate endcap (SAGE) architecture (right-hand side (b)), in accordance with an embodiment of the present disclosure. FIG. 10 illustrates cross-sectional views representing various operations in a method of fabricating a self-aligned gate endcap (SAGE) structure with gate-all-around devices, in accordance with an embodiment of the present disclosure. FIG. 11A illustrates a three-dimensional cross-sectional view of a nanowire-based integrated circuit structure, in accordance with an embodiment of the present disclosure. FIG. 11B illustrates a cross-sectional source or drain view of the nanowire-based integrated circuit structure of FIG. 11A, as taken along the a-a′ axis, in accordance with an embodiment of the present disclosure. FIG. 11C illustrates a cross-sectional channel view of the nanowire-based integrated circuit structure of FIG. 11A, as taken a