US-20260130209-A1 - SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

US20260130209A1US 20260130209 A1US20260130209 A1US 20260130209A1US-20260130209-A1

Abstract

A semiconductor device including a substrate, a semiconductor package, a thermal conductive bonding layer and a lid is provided. The semiconductor package is disposed on the substrate. The thermal conductive bonding layer is disposed on the semiconductor package. The lid is attached to the semiconductor package via the thermal conductive bonding layer. The lid has a first cavity and a second cavity connected to the first cavity. The semiconductor package is located in the first cavity, and the thermal conductive bonding layer is partially disposed in the second cavity. The second cavity has a first portion and a second portion joined with the first portion and narrower than the first portion, the second portion is located between the first portion and the first cavity, and the thermal conductive bonding layer is formed in the second portion. A method for manufacturing a semiconductor device is also provided.

Inventors

Yi-Huan LIAO
Po-Yuan Cheng
Chih-hao Chen
Pu Wang
Li-Hui Cheng

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date: 20260507
Application Date: 20241104

Claims (20)

1 . A semiconductor device, comprising: a substrate; a semiconductor package disposed on the substrate; a thermal conductive bonding layer disposed on the semiconductor package; and a lid attached to the semiconductor package via the thermal conductive bonding layer, wherein the lid has a first cavity and a second cavity connected to the first cavity, the semiconductor package is located in the first cavity, and the thermal conductive bonding layer is partially disposed in the second cavity, and wherein the second cavity has a first portion and a second portion joined with the first portion and narrower than the first portion, the second portion is located between the first portion and the first cavity, and the thermal conductive bonding layer is formed in the second portion.
2 . The semiconductor device of claim 1 , wherein the lid comprises: a plate portion; and a frame portion located at edges of the plate portion and protrudes towards the substrate, wherein a surface of the plate portion facing the semiconductor package is higher than the first cavity and lower than the second cavity.
3 . The semiconductor device of claim 1 , wherein the second cavity has a curved surface or an inclined surface.
4 . The semiconductor device of claim 1 , wherein a maximum width of the first portion is W 1 , a width of the second portion is W 2 , a maximum width of the thermal conductive bonding layer in the second cavity is WT, and W 2 <W 1 ≤WT.
5 . The semiconductor device of claim 1 , wherein a depth of the second cavity is D, a height of the thermal conductive bonding layer in the second cavity is H, and 0<H≤D.
6 . The semiconductor device of claim 1 , wherein the semiconductor package comprises an encapsulant, and the second cavity is overlapped with the encapsulant.
7 . The semiconductor device of claim 6 , wherein the semiconductor package further comprises a plurality of semiconductor dies laterally wrapped by the encapsulant, and the second cavity is overlapped with the encapsulant between two adjacent semiconductor dies among the plurality of semiconductor dies.
8 . The semiconductor device of claim 7 , wherein a width of the first portion is W 1 , a width of the second portion is W 2 , a width of the encapsulant between the two adjacent semiconductor dies is W 3 , and W 2 <W 1 ≤W 3 .
9 . A semiconductor device, comprising: a substrate; a semiconductor package disposed on the substrate, wherein the semiconductor package comprises at least one semiconductor die and an encapsulant laterally wrapping the at least one semiconductor die; a thermal conductive bonding layer disposed on the semiconductor package; and a lid attached to the semiconductor package via the thermal conductive bonding layer, wherein the lid has a first cavity and a second cavity connected to the first cavity, the semiconductor package is in the first cavity, and the thermal conductive bonding layer is partially in the second cavity, and wherein an orthogonal projection of the second cavity on the semiconductor package is overlapped with the encapsulant beside the at least one semiconductor die.
10 . The semiconductor device of claim 9 , wherein the second cavity is located over the encapsulant along a periphery of the semiconductor package.
11 . The semiconductor device of claim 9 , wherein the at least one semiconductor die includes a first die and a second die, and the orthogonal projection of the second cavity on the semiconductor package is located on the encapsulant between the first die and the second die.
12 . The semiconductor device of claim 9 , further comprising: a backside metal layer disposed between the thermal conductive bonding layer and the semiconductor package.
13 . The semiconductor device of claim 9 , wherein a width of the backside metal layer is smaller than a width of the thermal conductive bonding layer.
14 . The semiconductor device of claim 9 , wherein the lid comprises: a plate portion; and a frame portion located at edges of the plate portion and protrudes towards the substrate, wherein a surface of the plate portion facing the semiconductor package is higher than the first cavity and lower than the second cavity.
15 . The semiconductor device of claim 14 , further comprising: a bonding layer disposed between the substrate and the frame portion or between the substrate and the plate portion.
16 . The semiconductor device of claim 14 , further comprising: a passive component disposed between the frame portion and the semiconductor package.
17 . A method for manufacturing a semiconductor device, comprising: disposing a semiconductor package on a substrate; and attaching a lid to the semiconductor package via a thermal conductive bonding layer, wherein the lid has a first cavity and a second cavity connected to the first cavity, the semiconductor package is located in the first cavity, and the thermal conductive bonding layer is partially disposed in the second cavity, and wherein the second cavity has a first portion and a second portion joined with the first portion and narrower than the first portion, the second portion is located between the first portion and the first cavity, and the thermal conductive bonding layer is formed in the second portion.
18 . The method for manufacturing the semiconductor device of claim 17 , further comprising: attaching the lid to the substrate through a bonding layer.
19 . The method for manufacturing the semiconductor device of claim 18 , wherein the lid comprises: a plate portion; and a frame portion located at edges of the plate portion and protrudes towards the substrate, wherein the plate portion is attached to the substrate through the bonding layer.
20 . The method for manufacturing the semiconductor device of claim 19 , further comprising: disposing a passive component between the frame portion and the bonding layer.

Description

BACKGROUND A typical problem with miniaturization of semiconductor devices is heat dissipation during operation. A prolonged exposure of a die by operating at excessive temperatures may decrease the reliability and lifetime of the die. This problem may become severe if the die generates a lot of heat during operation. As such, improvements to heat dissipation are still needed. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 illustrates a top view of a semiconductor device in accordance with some embodiments of the present disclosure. FIG. 2 illustrates a cross-sectional view of a semiconductor device in accordance with some embodiments of the present disclosure. FIG. 3 illustrates an enlarged partial cross-sectional view of a semiconductor device in accordance with some embodiments of the present disclosure. FIG. 4 illustrates an enlarged partial cross-sectional view of a semiconductor device in accordance with some embodiments of the present disclosure. FIG. 5 illustrates an enlarged partial cross-sectional view of a semiconductor device in accordance with some embodiments of the present disclosure. FIG. 6 illustrates an enlarged partial cross-sectional view of a semiconductor device in accordance with some embodiments of the present disclosure. FIG. 7 illustrates a cross-sectional view of a semiconductor device in accordance with some embodiments of the present disclosure. FIG. 8 illustrates a flow chart of a method for manufacturing a semiconductor device in accordance with some embodiments of the present disclosure. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, it will be understood that when an element is referred to as being “connected to” or “coupled to” another element, it may be directly connected to or coupled to the other element, or one or more intervening elements may be present. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “on,” “over,” “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Thermal interface materials (TIMs) are materials inserted between two components in order to enhance the thermal coupling between them. For example, thermal interface materials can be inserted between heat-producing devices (e.g., integrated circuits) and heat-dissipating devices (e.g., heat sinks) to enhance the thermal dissipation performance. However, many factors in the manufacturing process, such as volume change of the thermal interface material layer caused by significant temperature change in the post reflow process (e.g., a ball mount process), poor outgassing during the post reflow process, inappropriate volume selection of the thermal interface material, etc., may lead to poor coverage of the thermal interface material layer. The poor coverage of the thermal interface material layer results in increased contact thermal resistance and/or reduced thermal dissipation performance. In addition, the stress generated at the interface between the heat-dissipating device (e.g., a lid) and the thermal interface material layer due to CTE (coefficient of thermal expansion) mismatch during the temperature variation processes (e.g., a thermal cycle testing process) can easily lead to cracks at the interf