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US-20260130210-A1 - PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME

US20260130210A1US 20260130210 A1US20260130210 A1US 20260130210A1US-20260130210-A1

Abstract

A package structure and method for forming the same are provided. The package structure includes a cooling substrate formed on a base substrate, and the cooling substrate includes a cooling device. The package structure includes a packaged semiconductor device formed on the cooling substrate, and the packaged semiconductor device includes a first die, and the cooling device is directly below the first die.

Inventors

  • Shih-Wei Liu
  • Tsun-Yen Wu
  • Sing-Da JIANG
  • Kathy Wei Yan

Assignees

  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date
20260507
Application Date
20241104

Claims (20)

  1. 1 . A package structure, comprising: a cooling substrate formed on a base substrate, wherein the cooling substrate comprises a cooling device; and a packaged semiconductor device formed on the cooling substrate, wherein the packaged semiconductor device comprises a first die, and the cooling device is directly below the first die.
  2. 2 . The package structure as claimed in claim 1 , wherein the cooling substrate comprises: a core substrate; a front side interconnect structure formed on the core substrate; and a back side interconnect structure formed below the core substrate, wherein the cooling device is formed in the front side interconnect structure.
  3. 3 . The package structure as claimed in claim 2 , wherein the cooling device is formed in the core substrate.
  4. 4 . The package structure as claimed in claim 2 , further comprising: another cooling device formed in the back side interconnect structure.
  5. 5 . The package structure as claimed in claim 1 , further comprising: a front side heat spreader formed on the packaged semiconductor device.
  6. 6 . The package structure as claimed in claim 1 , further comprising: a back side heat spreader formed below the cooling substrate, wherein the back side heat spreader comprises an extending portion through the base substrate, and the extending portion of the back side heat spreader is connected to the cooling substrate.
  7. 7 . The package structure as claimed in claim 1 , wherein the cooling substrate comprises a plurality of vias, and the vias are electrically connected to the cooling device.
  8. 8 . The package structure as claimed in claim 6 , further comprising: a back side fastening element connecting the base substrate and the back side heat spreader.
  9. 9 . The package structure as claimed in claim 1 , further comprising: a stiffener formed on the cooling substrate, wherein the packaged semiconductor device is surrounded by the stiffener.
  10. 10 . A package structure, comprising: a cooling substrate formed on a base substrate, wherein the cooling substrate comprises a thermal electronic cooler (TEC); a packaged semiconductor device formed on the cooling substrate, wherein the packaged semiconductor device comprises a first die; and a back side heat spreader formed below the cooling substrate, wherein the back side heat spreader comprises an extending portion through the base substrate, and the extending portion of the back side heat spreader is connected to the cooling substrate.
  11. 11 . The package structure as claimed in claim 10 , wherein the cooling substrate comprises a plurality of vias, and the vias are electrically connected to the thermal electronic cooler (TEC).
  12. 12 . The package structure as claimed in claim 10 , further comprising: a front side heat spreader formed on the packaged semiconductor device.
  13. 13 . The package structure as claimed in claim 12 , further comprising: a fastening element connecting the front side heat spreader and the back side heat spreader.
  14. 14 . The package structure as claimed in claim 10 , wherein the cooling substrate comprises: a first thermal interface material (TIM) on the packaged semiconductor device; a lid structure formed on the first TIM; a second TIM formed on the lid structure; and a front side heat spreader formed on the second TIM.
  15. 15 . The package structure as claimed in claim 10 , further comprising: a back side fastening element connecting the base substrate and the back side heat spreader.
  16. 16 . The package structure as claimed in claim 10 , wherein the first die comprises: a plurality of nanostructures; an S/D structure connected to the nanostructures; a gate structure wrapped around the nanostructures; and an inner spacer layer between the gate structure and the S/D structure.
  17. 17 . A method for forming a package structure, comprising: forming a front side interconnect structure over a core substrate; forming a cooling device in the front side interconnect structure or the core substrate to form a cooling substrate; bonding a packaged semiconductor device to the cooling substrate, wherein the packaged semiconductor device comprises a first die, and the cooling device is directly below the first die; and bonding the cooling substrate to a base substrate.
  18. 18 . The method for forming the package structure as claimed in claim 17 , further comprising: forming a front side heat spreader on the packaged semiconductor device.
  19. 19 . The method for forming the package structure as claimed in claim 17 , further comprising: forming a trench in the base substrate; and forming a back heat spreader in the trench and below the carrier substrate, wherein the back heat spreader comprises an extending portion that extends through the trench.
  20. 20 . The method for forming the package structure as claimed in claim 17 , further comprising: forming a back side interconnect structure below the base substrate; and forming another cooling device in the back side interconnect structure.

Description

BACKGROUND Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. Many integrated circuits are typically manufactured on a single semiconductor wafer, and individual dies on the wafer are singulated by sawing between the integrated circuits along a scribe line. The individual dies are typically packaged separately, in multi-chip modules, for example, or in other types of packaging. New packaging technologies, such as package on package (PoP), have begun to be developed, in which a top package with a device die is bonded to a bottom package, with another device die. By adopting the new packaging technologies, various packages with different or similar functions may be integrated together. Although existing package structures and methods of fabricating package structure have generally been adequate for their intended purposes, they have not been entirely satisfactory in all respects. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIGS. 1A-1O show cross-sectional representations of various stages of forming a package structure, in accordance with some embodiments of the disclosure. FIG. 2 shows a cross-sectional representation of the cooling device, in accordance with some embodiments of the disclosure. FIG. 3 shows a top view of the semiconductor dies and the stacked dies of FIG. 1D, in accordance with some embodiments of the disclosure. FIG. 4 shows a top view of the semiconductor dies and the stacked dies of FIG. 1L, in accordance with some embodiments of the disclosure. FIG. 5 shows a bottom view of the conducive connectors below the cooling substrate of FIG. 1O, in accordance with some embodiments of the disclosure. FIGS. 6A-6C show bottom views of the trench, the openings of FIG. 1N, in accordance with some embodiments of the disclosure. FIG. 7 shows a cross-sectional representation of a package structure, in accordance with some embodiments of the disclosure FIG. 8 shows a cross-sectional representation of a package structure, in accordance with some embodiments of the disclosure. FIG. 9 shows a cross-sectional representation of a package structure, in accordance with some embodiments of the disclosure. FIG. 10 shows a cross-sectional representation of a package structure, in accordance with some embodiments of the disclosure. FIGS. 11A-11G shows a cross-sectional representation of a package structure, in accordance with some embodiments of the disclosure. FIG. 12 shows a cross-sectional representation of a package structure, in accordance with some embodiments of the disclosure. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Some variations of the embodiments are described. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. It should be understood that additional operations can be provided before, during, and after the method, and some of the operations described can be replaced or eliminated for other embodiments of the method. The gate all around (GAA) transistor structures described below may be patterned by any suitable method. For example, the structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes