US-20260130213-A1 - SEMICONDUCTOR MODULE

US20260130213A1US 20260130213 A1US20260130213 A1US 20260130213A1US-20260130213-A1

Abstract

A semiconductor module includes: a cooler; a substrate above the cooler and an insulating base material, a front surface conductor on one surface of the insulating base material, and a rear surface conductor on a rear surface of the insulating base material; a thermal-conductive member disposed between the cooler and the rear surface conductor; and a plurality of semiconductor elements each having a first main electrode joined to the front surface conductor and a second main electrode disposed on a surface opposite to a surface on which the first main electrode is disposed. Wiring patterns of the front surface conductor include one or more element mounting portions to which the first main electrodes of the semiconductor elements aligned in a predetermined direction are commonly connected. One of the element mounting portions is disposed in a central region of the substrate in an orthogonal direction orthogonal to the predetermined direction.

Inventors

Tomoaki MITSUNAGA
Masayoshi Nishihata

Assignees

DENSO CORPORATION

Dates

Publication Date: 20260507
Application Date: 20260102
Priority Date: 20230705

Claims (7)

1 . A semiconductor module comprising: a cooler; a substrate disposed above the cooler, the substrate including an insulating base material, a front surface conductor disposed on one surface of the insulating base material and patterned, and a rear surface conductor disposed on a rear surface of the insulating base material opposite to the one surface; a thermal-conductive member disposed between the cooler and the rear surface conductor; and a plurality of semiconductor elements having a first main electrode joined to the front surface conductor and a second main electrode disposed on a surface opposite to a surface on which the first main electrode is disposed, wherein the front surface conductor includes a plurality of wiring patterns, the plurality of wiring patterns include one or more element mounting portions to which the first main electrodes of the plurality of semiconductor elements, which are aligned in a predetermined direction, are commonly connected, and one of the element mounting portions is disposed in a central region of the substrate in an orthogonal direction orthogonal to the predetermined direction.
2 . The semiconductor module according to claim 1 , wherein the front surface conductor is patterned into the plurality of wiring patterns in the orthogonal direction.
3 . The semiconductor module according to claim 2 , wherein the substrate has a non-disposition region in which the front surface conductor is not disposed on the one surface, and the non-disposition region extends in the predetermined direction between the wiring patterns.
4 . The semiconductor module according to claim 1 , wherein the plurality of semiconductor elements include a plurality of upper arm elements and a plurality of lower arm elements, the plurality of upper arm elements provide an upper arm of an upper and lower arm circuit and are aligned in the predetermined direction, the plurality of lower arm elements provide a lower arm of the upper and lower arm circuit and are aligned in the predetermined direction, the one or more element mounting portions include an upper arm mounting portion to which the first main electrodes of the plurality of upper arm elements are commonly connected, and a lower arm mounting portion to which the first main electrodes of the plurality of lower arm elements are commonly connected, and one of the upper arm mounting portion or the lower arm mounting portion is disposed in the central region in the orthogonal direction, and an other of the upper arm mounting portion or the lower arm mounting portion is disposed outside the central region.
5 . The semiconductor module according to claim 4 , wherein the front surface conductor includes, as main wiring portions, an upper arm wiring portion electrically connected to the first main electrodes of the upper arm elements through the upper arm mounting portion, and a lower arm wiring portion electrically connected to the second main electrodes of the lower arm elements, and one of the main wiring portions, which is electrically isolated from the semiconductor elements disposed in the central region, is disposed between the upper arm mounting portion and the lower arm mounting portion in the orthogonal direction.
6 . The semiconductor module according to claim 4 , wherein among the one or more element mounting portions, the element mounting portion disposed in the central region has an area smaller than an area of the element mounting portion disposed outside the central region, in a plan view when viewed in a thickness direction of the substrate.
7 . The semiconductor module according to claim 1 , wherein a thickness of the front surface conductor is greater than a thickness of the rear surface conductor.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS The present application is a continuation application of International Patent Application No. PCT/JP2024/020604 filed on June 6, 2024, which designated the U.S. and claims the benefit of priority from Japanese Patent Application No. 2023-110774 filed on July 5, 2023. The entire disclosures of all of the above applications are incorporated herein by reference. TECHNICAL FIELD The present disclosure herein relates to a semiconductor module. BACKGROUND JP 2002-153079 A discloses a semiconductor module. Contents of the description of JP 2002-153079 A are incorporated herein by reference as a description of technical elements in this description. SUMMARY According to an aspect of the present disclosure, a semiconductor module includes a cooler, a substrate, a thermal-conductive member, and a plurality of semiconductor elements. The substrate is disposed above the cooler. The substrate includes an insulating base material, a front surface conductor disposed on one surface of the insulating base material and patterned, and a rear surface conductor disposed on a rear surface of the insulating base material opposite to the one surface. The thermal-conductive member is disposed between the cooler and the rear surface conductor. Each of the plurality of semiconductor elements has a first main electrode joined to the front surface conductor and a second main electrode disposed on a surface opposite to a surface on which the first main electrode is disposed. The front surface conductor may include a plurality of wiring patterns. The plurality of wiring patterns may include one or more element mounting portions to which the first main electrodes of the plurality of semiconductor elements, which are aligned in a predetermined direction, are commonly connected. One of the element mounting portions may be disposed in a central region of the substrate in an orthogonal direction orthogonal to the predetermined direction. BRIEF DESCRIPTION OF DRAWINGS Features and advantages of the present disclosure will become more apparent from the following detailed description made with reference to the accompanying drawings. FIG. 1 is a diagram illustrating a circuit configuration of a power conversion device to which a semiconductor device according to a first embodiment is applied. FIG. 2 is a perspective view illustrating an example of a semiconductor module. FIG. 3 is a plan view of the semiconductor module. FIG. 4 is a cross-sectional view taken along a line IV-IV in FIG. 3. FIG. 5 is a plan view illustrating an example of the semiconductor device. FIG. 6 is a plan view illustrating a wiring pattern of a substrate. FIG. 7 is a cross-sectional view taken along a line VII-VII in FIG. 5. FIG. 8 is a cross-sectional view illustrating another example of the connection structure between a capacitor and the substrate. FIG. 9 is a cross-sectional view illustrating still another example of the connection structure between the capacitor and the substrate. FIG. 10 is a cross-sectional view illustrating still another example of the connection structure between the capacitor and the substrate. FIG. 11 is a circuit diagram illustrating a verification model. FIG. 12 is a diagram illustrating a verification result. FIG. 13 is a diagram illustrating a temperature distribution. FIG. 14 is a diagram illustrating disposition of a current path formed by a snubber circuit. FIG. 15 is a plan view illustrating a modification example. FIG. 16 is a plan view illustrating another modification example. FIG. 17 is a plan view illustrating still another modification example. FIG. 18 is a plan view illustrating a semiconductor element in a semiconductor device according to a second embodiment. FIG. 19 is a cross-sectional view taken along a line XIX-XIX in FIG. 18. FIG. 20 is a partial cross-sectional view of the semiconductor device and a semiconductor module. FIG. 21 is a plan view illustrating an example of a connection structure between a clip and the semiconductor element. FIG. 22 is a cross-sectional view taken along a line XXII-XXII in FIG. 21. FIG. 23 is a plan view illustrating another example of the connection structure between the clip and the semiconductor element. FIG. 24 is a perspective view illustrating the clip. FIG. 25 is a plan view illustrating another example of the clip. FIG. 26 is a plan view illustrating still another example of the clip. FIG. 27 is a cross-sectional view illustrating still another example of the clip. FIG. 28 is a plan view illustrating still another example of the clip. FIG. 29 is a plan view illustrating still another example of the connection structure between the clip and the semiconductor element. FIG. 30 is a cross-sectional view taken along a line XXX-XXX in FIG. 29. FIG. 31 is a plan view illustrating still another example of the clip. FIG. 32 is a plan view illustrating still another example of the clip. FIG. 33 is a plan view illustrating still another example of the clip.