US-20260130215-A1 - THERMALLY ENHANCED FLIP CHIP DIES, MULTI-CHIP MODULE ASSEMBLY, AND METHODS OF FORMING SAME

Abstract

A method of fabricating flip chip dies comprising fabricating or providing a wafer including one or more component circuits, a front side having a plurality of metal bumps, a back side, and one or more wafer streets for dicing the wafer; mounting the wafer on a temporary wafer carrier via the metal bumps, depositing a copper layer on the back side of the wafer; defining one or more streets in the copper layer, the one or more streets being aligned with the one or more wafer streets, dicing the wafer into a plurality of singulated flip chip dies each having a component circuit of the one or more component circuits, and removing the plurality of singulated flip chip dies from the temporary wafer carrier. A method for fabricating a multi-chip module assembly, and a multi-chip module assembly is also provided.

Inventors

• Patrick Marcus Naraine
• Guillaume Alexandre Blin
• Grant Darcy Poulin
• Raymond Mitchell Waugh
• Kezia Cheng

Assignees

• SKYWORKS SOLUTIONS, INC.

Dates

Publication Date

20260507

Application Date

20251027

Claims (20)

1. 1 . A method of fabricating flip chip dies, the method comprising: fabricating or providing a wafer including one or more component circuits, a front side having a plurality of metal bumps, a back side, and one or more wafer streets for dicing the wafer; mounting the wafer on a temporary wafer carrier via the metal bumps; depositing a copper layer on the back side of the wafer; defining one or more streets in the copper layer, the one or more streets being aligned with the one or more wafer streets; dicing the wafer into a plurality of singulated flip chip dies each having a component circuit of the one or more component circuits; and removing the plurality of singulated flip chip dies from the temporary wafer carrier.
2. 2 . The method of claim 1 further comprising opening the one or more wafer streets and the one or more streets in the copper layer prior to dicing the wafer.
3. 3 . The method of claim 1 wherein depositing the copper layer on the back side of the wafer includes depositing the copper layer using a screen printing process.
4. 4 . The method of claim 3 wherein depositing the copper layer using the screen printing process includes depositing the copper layer as two or more layers.
5. 5 . The method of claim 1 wherein the one or more component circuits comprises one or more power amplifier circuits, switch circuits, control circuits, or filter circuits.
6. 6 . The method of claim 1 wherein depositing the copper layer and defining the one or more streets in the copper layer includes one of selectively depositing the copper layer on the back side of the wafer to define the one or more streets in the copper layer or using a wafer mask to define the one or more streets.
7. 7 . The method of claim 1 wherein defining the one or more streets in the copper layer comprises laser drilling the one or more streets in the copper layer.
8. 8 . The method of claim 1 wherein the copper layer has a thickness of at least 50 micrometers.
9. 9 . The method of claim 1 wherein mounting the wafer on the temporary wafer carrier includes temporarily adhering the metal bumps to the temporary wafer carrier with an adhesive.
10. 10 . The method of claim 1 wherein the wafer includes a compound semiconductor or a piezoelectric layer.
11. 11 . A method of fabricating a multi-chip module assembly, the method comprising: mounting a flip chip die including a component circuit, a front side having a plurality of metal bumps, and a back side on a multi-chip module via the plurality of metal bumps; stacking a silicon die on the back side of the flip chip die; overmolding the multi-chip module, a thickness of the overmold at least covering the silicon die; reducing a thickness of the overmold such that a surface of the silicon die is exposed through the overmold; and depositing or attaching a metal layer at least covering a front side of the multi-chip module, the front side including the surface of the silicon die.
12. 12 . The method of claim 11 further comprising grinding the silicon die to a predetermined thickness and dicing the silicon die to a predetermined length and width prior to stacking the silicon die, one or both of the predetermined length and width being greater than a respective length and width of the flip chip die.
13. 13 . The method of claim 11 wherein stacking the silicon die on the back side of the flip chip die includes adhering the silicon die to the flip chip die with a thermally conductive adhesive.
14. 14 . The method of claim 11 wherein the metal layer is a copper layer.
15. 15 . The method of claim 14 wherein depositing or attaching the copper layer includes using a copper plating process or a screen printing process.
16. 16 . The method of claim 11 wherein depositing or attaching the metal layer further comprises depositing or attaching the metal layer over and enclosing the multi-chip module, the metal layer being in contact with a peripheral boundary of the multi-chip module.
17. 17 . The method of claim 11 wherein reducing the thickness of the overmold includes back-grinding the overmold such that the surface of the silicon die is exposed.
18. 18 . The method of claim 11 wherein the component circuit comprises one of a power amplifier circuit, a switch circuit, a control circuit, or a filter circuit.
19. 19 . The method of claim 11 wherein the flip chip die includes one or more through wafer vias configured to electrically couple the front side of the flip chip die to the back side of the flip chip die.
20. 20 . The method of claim 11 wherein the flip chip die includes a compound semiconductor or a piezoelectric layer.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority under 35 U.S.C. § 119(e) to U.S. Provisional Patent Application Ser. No. 63/716,764, titled “METHOD OF FABRICATING A THERMALLY ENHANCED MULTI-CHIP MODULE ASSEMBLY,” filed Nov. 6, 2024, and to U.S. Provisional Patent Application Ser. No. 63/716,767, titled “METHOD OF FABRICATING THERMALLY ENHANCED FLIP CHIP DIES AND MULTI-CHIP MODULE ASSEMBLY,” filed Nov. 6, 2024, the entire content of each being incorporated herein by reference for all purposes. BACKGROUND Field of Technology The present disclosure relates generally to methods of fabricating flip chip dies and a multi-chip module assembly. More specifically, the present disclosure relates to methods of fabricating flip chip dies and a multi-chip module assembly having improved thermal performance. Description of the Related Technology Flip chip die are typically directly connected to carriers (e.g., substrates, circuit boards, and the like) via conductive bumps that are placed on the surface of the dies. In contrast to traditional wire bonding techniques, interconnection between the flip chip die and the carrier occurs via the conductive bumps. The die having conductive bumps is flipped and placed face down so that conductive bumps are directly attached to the carrier, thereby forming a flip chip package or a module. One advantage of flip chip packages is that they are typically smaller than traditional wire bonded packages with the same functionality. The size of such packages can be significant for portable electronic devices, such as cellular phones, smart phones, portable MP3 players, and the like. As sizes of flip chip packages continue to decrease, improving their thermal performance becomes even more significant. Therefore, there exists a need to provide efficient top-side cooling of a flip chip die. SUMMARY According to one aspect of the present disclosure, there is provided a method of fabricating flip chip dies. The method comprises fabricating or providing a wafer including one or more component circuits, a front side having a plurality of metal bumps, a back side, and one or more wafer streets for dicing the wafer, mounting the wafer on a temporary wafer carrier via the metal bumps, depositing a copper layer on the back side of the wafer, defining one or more streets in the copper layer, the one or more streets being aligned with the one or more wafer streets, dicing the wafer into a plurality of singulated flip chip dies each having a component circuit of the one or more component circuits, and removing the plurality of singulated flip chip dies from the temporary wafer carrier. In one example, the method further comprises opening the one or more wafer streets and the one or more streets in the copper layer prior to dicing the wafer. In one example, depositing the copper layer on the back side of the wafer includes depositing the copper layer using a copper plating process or a screen printing process. In one example, the one or more component circuits comprises one or more power amplifier circuits, switch circuits, control circuits, or filter circuits. In one example, depositing the copper layer using the screen printing process includes depositing the copper layer as two or more layers. In one example, depositing the copper layer and defining the one or more streets in the copper layer includes selectively depositing the copper layer on the back side of the wafer to define the one or more streets in the copper layer. In one example, defining the one or more streets in the copper layer includes using a wafer mask to define the one or more streets. In one example, defining the one or more streets in the copper layer comprises laser drilling the one or more streets in the copper layer. In one example, the copper layer has a thickness of at least 50 micrometers. In one example, the wafer includes one or more through wafer vias configured to electrically couple the front side of the wafer to the back side of the wafer. In one example, mounting the wafer on the temporary wafer carrier includes temporarily adhering the metal bumps to the temporary wafer carrier with an adhesive. In one example, the temporary wafer carrier is a silicon temporary wafer carrier. In one example, the wafer includes a compound semiconductor or a piezoelectric layer. According to another aspect of the present disclosure, there is provided a method of fabricating or providing a singulated flip chip die including one or more component circuit, the singulated flip chip die including a front side having a plurality of metal bumps, and a back side having a copper layer, mounting the singulated flip chip die on a multi-chip module via the metal bumps, overmolding the multi-chip module, a thickness of the overmold at least covering the copper layer, and reducing the thickness of the overmold such that a surface of the copper layer is exposed through the overmold. In one example, fabricating or providing the