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US-20260130217-A1 - INTEGRATED TEMPERATURE CONTROL SYSTEM FOR SUBASSEMBLIES

US20260130217A1US 20260130217 A1US20260130217 A1US 20260130217A1US-20260130217-A1

Abstract

Embodiments herein provide for an integrated thermal control assembly comprising: a semiconductor device; a cold plate stacked vertically adjacent to the semiconductor device; and a heater device disposed adjacent to the semiconductor device and the cold plate.

Inventors

  • Rajesh Katkar
  • Ron Zhang
  • Guilian Gao
  • Thomas Workman

Assignees

  • ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Dates

Publication Date
20260507
Application Date
20241127

Claims (20)

  1. 1 . An integrated thermal control assembly comprising: a semiconductor device; a cold plate stacked vertically adjacent to the semiconductor device; and a heater device disposed adjacent to the semiconductor device and the cold plate.
  2. 2 . The integrated thermal control assembly of claim 1 , wherein the cold plate comprises: a perimeter sidewall; a top portion; a cavity divider; and coolant channels, wherein the perimeter sidewall and the cavity divider extend downwardly from the top portion to define portions of the coolant channels.
  3. 3 . The integrated thermal control assembly of claim 1 , wherein the semiconductor device is a laser device.
  4. 4 . The integrated thermal control assembly of claim 1 , wherein the semiconductor device is a light emitting diode (LED) device.
  5. 5 . The integrated thermal control assembly of claim 1 , wherein the cold plate and the heater device collectively control a temperature of the semiconductor device.
  6. 6 . The integrated thermal control assembly of claim 5 , wherein the cold plate and the heater device collectively control the temperature of the semiconductor device to remain within a predetermined range of 50 degrees Celsius to 75 degrees Celsius.
  7. 7 . The integrated thermal control assembly of claim 3 , wherein the laser device is a laser diode, a fabry-perot laser, a distributed feedback laser, a vertical cavity surface-emitting laser, or a quantum dot laser.
  8. 8 . The integrated thermal control assembly of claim 1 , wherein the semiconductor device is a micro-electromechanical systems (MEMs) device.
  9. 9 . The integrated thermal control assembly of claim 1 , wherein: the semiconductor device, the cold plate, and the heater device are vertically stacked with the heater device disposed between the semiconductor device and the cold plate; the cold plate is attached to a first side of the heater device; the semiconductor device is attached to a second side of the heater device opposite the first side of the heater device; and the first side of the heater device is exposed to at least one coolant channel.
  10. 10 . The integrated thermal control assembly of claim 9 , wherein the heater device is attached to the cold plate and the semiconductor device by direct dielectric bonds or direct hybrid bonds.
  11. 11 . The integrated thermal control assembly of claim 1 , wherein: the semiconductor device, and the heater device are vertically stacked with the cold plate disposed between the semiconductor device and the heater device; the heater device is attached to a first side of the cold plate; the semiconductor device is attached to a second side of the cold plate opposite the first side of the cold plate; and a backside of the semiconductor device is exposed to at least one coolant channel.
  12. 12 . The integrated thermal control assembly of claim 11 , wherein the cold plate is attached to the heater device and the semiconductor device by direct dielectric bonds or direct hybrid bonds.
  13. 13 . The integrated thermal control assembly of claim 3 , further comprising an optical waveguide disposed adjacent to the laser device.
  14. 14 . The integrated thermal control assembly of claim 1 , wherein: the semiconductor device, the cold plate, and the heater device are vertically stacked with the semiconductor device disposed between the cold plate and the heater device; the heater device is attached to a frontside of the semiconductor device; the cold plate is attached to a backside of the semiconductor device opposite the frontside of the semiconductor device; and the backside of the semiconductor device is exposed to at least one coolant channel.
  15. 15 . The integrated thermal control assembly of claim 14 , wherein the semiconductor device is attached to a first side of the heater device and an optical waveguide is attached to a second side of the heater device opposite the first side of the heater device; and the heater device comprises an internal sidewall defining a cavity to expose a portion of the semiconductor device to a portion of the optical waveguide.
  16. 16 . The integrated thermal control assembly of claim 14 , wherein the semiconductor device is attached to the heater device and the cold plate by direct dielectric bonds or direct hybrid bonds.
  17. 17 . The integrated thermal control assembly of claim 1 , wherein: the semiconductor device is disposed laterally adjacent to the heater device; and the cold plate is attached to a first side of the heater device and a first side of the semiconductor device.
  18. 18 . The integrated thermal control assembly of claim 17 , wherein the cold plate is attached to the heater device and the semiconductor device by direct dielectric bonds or direct hybrid bonds.
  19. 19 . The integrated thermal control assembly of claim 1 , a width of the cold plate in a first direction is greater than: a width of the heater device in the first direction, a width of the semiconductor device in the first direction, or a combined width of the heater device and the semiconductor device in the first direction, wherein the first direction is perpendicular to a second direction in which the perimeter sidewall extends.
  20. 20 . The integrated thermal control assembly of claim 1 , wherein the semiconductor device is a first semiconductor device and the integrated thermal control assembly further comprises: a second semiconductor device disposed laterally adjacent to the first semiconductor device, and wherein: the cold plate is disposed vertically adjacent to the first semiconductor device, the second semiconductor device and the heater device.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims the benefit of U.S. Provisional Patent Application No. 63/716,416, filed Nov. 5, 2024, which is hereby incorporated by reference herein in its entirety. FIELD The present disclosure relates to advanced packaging for microelectronic devices, and in particular, temperature control systems for device packages and methods of manufacturing the same. BACKGROUND Energy consumption poses a critical challenge for the future of large-scale computing as the world's computing energy requirements are rising at a rate that most would consider unsustainable. Some models predict that the information, communication and technology (ICT) ecosystem could exceed 20% of global electricity use by 2030, with direct electrical consumption by large-scale computing centers accounting for more than one-third of that energy usage. A significant portion of the energy used by such large-scale computing centers is devoted to cooling, since even small increases in operating temperatures can negatively impact the performance of microprocessors, memory devices, and other electronic components. While some of this energy is expended to operate the cooling systems that are directly cooling the chips (e.g., heat spreaders, heat pipes, etc.), energy consumption/costs for indirect cooling can also be quite staggering. Indirect cooling energy costs include, for example, cooling or air conditioning of data center buildings. Data center buildings can house thousands, to tens of thousands or more, of high performance chips in server racks, and each of those high performance chips is a heat source. An uncontrolled ambient temperature in a data center will adversely affect the performance of the individual chips, and the data center system performance as a whole. Thermal dissipation in high-power density chips (semiconductor devices/die) is also a critical challenge as improvements in chip performance, e.g., through increased gate or transistor density due to advanced processing nodes, evolution of multi-core microprocessors, etc., have resulted in increased power density and a corresponding increase in thermal flux that contributes to elevated chip temperatures. Higher density of transistors also increases the length of metal wiring on the chips, which generates its own additional thermal flux due to Joule heating of these wires due to higher currents. These elevated temperatures are undesirable as they can degrade the chip's operating performance, efficiency, reliability, and amount of remaining life. Cooling systems used to maintain the chip at a desired operating temperature typically remove heat using one or more heat dissipation devices, e.g., thermal spreaders, heat pipes, cold plates, liquid cooled heat pipe systems, thermal-electric coolers, heat sinks, etc. One or more thermal interface materials (TIMs), such as, for example, thermal paste, thermal adhesive, or thermal gap filler, may be used to facilitate heat transfer between the surfaces of a chip and heat dissipation device(s). A thermal interface materials is any material that is inserted between two components to enhance the thermal coupling therebetween. Unfortunately, the combined thermal resistance of (i) the interfacial boundary regions between one or more TIMs and the chip and/or the heat dissipation device(s), and (ii) the thermal interface material itself can inhibit heat transfer from the chip to the heat dissipation devices, undesirably reducing the cooling efficiency of the cooling system. Generally speaking, there are multiple components between the heat dissipating sources (i.e., active circuitry) in the chips and the heat dissipation devices, each of which contributes to the system thermal resistance cumulatively along the heat transfer paths and raises chip junction temperatures from the ambient. Such cooling systems can suffer from reduced cooling efficiency due to the design and manufacture of system components. Additionally, communication between electronic components on a server rack, and between server racks themselves, is generally provided by copper wires. Unfortunately, these copper wires suffer from problems such as heat dissipation (due to their intrinsic resistance to current), communication signal attenuation, and bandwidth loss. As data demands grow, copper-based Serializer/Deserializer (SerDes) circuitry, which connects switching application-specific integrated circuits (ASICs) to pluggable transceivers, may be used to enable faster transmission, but faster ASICs require improved copper connections through more channels or higher speeds. However, as link density and bandwidth increase, a significant portion of system power and cost is consumed by driving signals from the ASICs to optical interconnects at the edge of the rack. The size limitations of ASIC ball grid array (BGA) packages (e.g. due to warpage concerns), require higher SerDes speeds to support increased bandwidth. This also results in h