US-20260130221-A1 - SEMICONDUCTOR PACKAGE

US20260130221A1US 20260130221 A1US20260130221 A1US 20260130221A1US-20260130221-A1

Abstract

A semiconductor package is provided. The semiconductor package includes a base chip, a plurality of first semiconductor chips stacked on the base chip, a dummy chip stacked on an uppermost first semiconductor chip of the plurality of first semiconductor chips, and a molding structure surrounding the base chip, the plurality of first semiconductor chips, and the dummy chip, wherein the dummy chip includes a channel extending from an upper surface of the dummy chip to a lower surface of the dummy chip, the channel has a shape extending from a center of the dummy chip to at least any one point located at an edge of the dummy chip, in a horizontal direction in a top view, and the molding structure fills the channel.

Inventors

Hyeonmin Lee
HYUNGCHUL SHIN

Assignees

SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date: 20260507
Application Date: 20251103
Priority Date: 20241105

Claims (20)

1 . A semiconductor package comprising: a base chip; a plurality of first semiconductor chips on the base chip; a dummy chip on an uppermost first semiconductor chip of the plurality of first semiconductor chips; and a molding structure surrounding the base chip, the plurality of first semiconductor chips, and the dummy chip, wherein the dummy chip comprises a channel extending from an upper surface of the dummy chip to a lower surface of the dummy chip along a first direction, the channel extending from a center of the dummy chip to an edge of the dummy chip along a second direction perpendicular to the first direction, and wherein the molding structure is disposed at the channel.
2 . The semiconductor package of claim 1 , wherein the channel comprises: a first portion having an X shape in a plane perpendicular to the first direction, the first portion extending from the center of the dummy chip to four vertices of the dummy chip; and a second portion having a rectangular ring shape in the plane, the second portion partially overlapping the first portion.
3 . The semiconductor package of claim 1 , wherein the channel comprises: a first portion having a plus sign shape in a plane perpendicular to the first direction, the first portion extending from the center of the dummy chip to centers of four sides of the dummy chip; and a second portion having a rectangular ring shape in the plane, the second portion partially overlapping the first portion.
4 . The semiconductor package of claim 1 , wherein the channel comprises: a first portion having an X shape in a plane perpendicular to the first direction, the first portion extending from the center of the dummy chip to four vertices of the dummy chip; a second portion having a plus sign shape in the plane, the second portion extending from the center of the dummy chip to centers of four sides of the dummy chip; and a third portion having a rectangular ring shape in the plane.
5 . The semiconductor package of claim 1 , wherein the channel comprises a first part and a second part stacked along the first direction, and wherein a width of the first part of the channel along the second direction is different from a width of the second part of the channel along the second direction.
6 . The semiconductor package of claim 5 , wherein a cross-section of the channel in a plane that is parallel to the first direction has a trapezoidal shape, and wherein the width of the channel along the second direction gradually decreases towards the uppermost first semiconductor chip.
7 . The semiconductor package of claim 1 , wherein a volume of the molding structure disposed at the channel is within a range of about 1 % to about 3 % of a total volume of the dummy chip.
8 . The semiconductor package of claim 1 , wherein an upper surface of the molding structure disposed at the channel is coplanar with the upper surface of the dummy chip.
9 . The semiconductor package of claim 1 , wherein the dummy chip is insulated from the uppermost first semiconductor chip.
10 . The semiconductor package of claim 1 , wherein the plurality of first semiconductor chips is free of a bump between adjacent first semiconductor chips of the plurality of first semiconductor chips.
11 . A semiconductor package comprising: a base chip; a plurality of first semiconductor chips on the base chip along a first direction; and a dummy chip on an uppermost first semiconductor chip of the plurality of first semiconductor chips, the dummy chip having a channel extending upward from a lower surface of the dummy chip, wherein the channel extends from a center of the dummy chip to at least four points located at an edge of the dummy chip, wherein the plurality of first semiconductor chips are stacked through direct bonding, and wherein the dummy chip is insulated from the uppermost first semiconductor chip.
12 . The semiconductor package of claim 11 , wherein the channel extends from a lower surface of the dummy chip to an upper surface of the dummy chip along the first direction, wherein the channel comprises a first part and a second part arranged on the first part along the first direction, the first part being between the second part and the uppermost first semiconductor chip along the first direction, and wherein a width of the first part along a second direction perpendicular to the first direction is constant, and a width of the second part along the second direction gradually increases towards the upper surface of the dummy chip.
13 . The semiconductor package of claim 11 , wherein the channel extends from a lower surface of the dummy chip to an upper surface of the dummy chip along the first direction, wherein a cross-section of the channel in a plane parallel to the first direction has a trapezoidal shape, and wherein a width of the channel along a second direction gradually decreases from the upper surface of the dummy chip towards the lower surface of the dummy chip, the second direction being perpendicular to the first direction.
14 . The semiconductor package of claim 11 , wherein the channel comprises: a first portion having an X shape in a plane perpendicular to the first direction, the first portion extending from the center of the dummy chip to four vertices of the dummy chip; and a second portion having a rectangular ring shape in the plane, the second portion partially overlapping the first portion.
15 . The semiconductor package of claim 11 , wherein the channel comprises: a first portion having a plus sign shape in a plane perpendicular to the first direction, the first portion extending from the center of the dummy chip to centers of four sides of the dummy chip; and a second portion having a rectangular ring shape in the plane, the second portion partially overlapping the first portion.
16 . The semiconductor package of claim 11 , wherein the channel comprises: a first portion having an X shape in a plane perpendicular to the first direction, the first portion extending from the center of the dummy chip to four vertices of the dummy chip; and a second portion having a plus sign shape in the plane, the second portion extending from the center of the dummy chip to centers of four sides of the dummy chip; and a third portion having a rectangular ring shape in the plane.
17 . A semiconductor package comprising: a first substrate; a base chip on the first substrate along a first direction; a plurality of first semiconductor chips stacked on the base chip along the first direction; a dummy chip on an uppermost first semiconductor chip of the plurality of first semiconductor chips, the dummy chip having a channel extending from a lower surface of the dummy chip to an upper surface of the dummy chip along the first direction; a first molding structure surrounding the base chip, the plurality of first semiconductor chips, and the dummy chip, the first molding structure filling the channel; and a second molding structure surrounding side surfaces of the first molding structure and the base chip on the first substrate wherein a semiconductor chip pad and a dielectric layer surrounding a side surface of the semiconductor chip pad are on each of lower surfaces and upper surfaces of the plurality of first semiconductor chips, wherein the channel extends from a center of the dummy chip to at least four points located at an edge of the dummy chip in a first plane perpendicular to the first direction, and wherein an upper surface of the first molding structure is coplanar with the upper surface of the dummy chip.
18 . The semiconductor package of claim 17 , wherein a cross-section of the channel in a second plane parallel to the first direction has a trapezoidal shape, and a width of the channel along a second direction gradually decreases towards the uppermost first semiconductor chip, the second direction being perpendicular to the first direction.
19 . The semiconductor package of claim 17 , wherein the channel comprises: a first portion having an X shape in the first plane, the first portion extending from the center of the dummy chip to four vertices of the dummy chip; a second portion having a plus sign shape in the first plane, the second portion extending from the center of the dummy chip to centers of four sides of the dummy chip; and a third portion having a rectangular ring shape in the first plane.
20 . The semiconductor package of claim 17 , comprising: an interposer between the first substrate and the base chip; and a second semiconductor chip on the interposer, the second semiconductor chip being spaced apart from the base chip along a second direction perpendicular to the first direction.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is based on and claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2024-0155691, filed on November 5, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety. BACKGROUND Recently, the demand for portable devices has rapidly increased in the electronics product market, and accordingly, miniaturization and lightening of electronic components mounted in electronic products have been continuously demanded. For miniaturization and lightening of electronic components, semiconductor packages mounted in the electronic components have been demanded to process high-capacity data with a small volume and reduced defects. In addition, a semiconductor package can have a plurality of semiconductor chips stacked in the vertical direction to reduce the size of the semiconductor package. However, when a plurality of semiconductor chips are hybrid-bonded, the structural reliability of a semiconductor package may decrease. SUMMARY The present disclosure provides a semiconductor package with improved reliability. In addition, the problems to be solved by the technical idea of the present disclosure are not limited to the problem mentioned above, and other problems could be clearly understood by those of ordinary skill in the art from the description below. To solve the technical problems of the present disclosure, the following semiconductor packages are provided. According to an aspect of the present disclosure, a semiconductor package includes a base chip, a plurality of first semiconductor chips stacked on the base chip, a dummy chip stacked on an uppermost first semiconductor chip among the plurality of first semiconductor chips, and a molding member surrounding the base chip, the plurality of first semiconductor chips, and the dummy chip, wherein the dummy chip includes a channel extending from an upper surface of the dummy chip to a lower surface of the dummy chip, the channel has a shape extending from a center of the dummy chip to at least any one point located at an edge of the dummy chip, in a horizontal direction in a top view, and the molding member fills the channel. According to another aspect of the present disclosure, a semiconductor package includes a base chip, a plurality of first semiconductor chips stacked on the base chip, and a dummy chip stacked on an uppermost first semiconductor chip among the plurality of first semiconductor chips and having a channel extending upward from a lower surface of the dummy chip, wherein the channel extends from a center of the dummy chip to at least four points located at an edge of the dummy chip, in a top view, the plurality of first semiconductor chips are stacked through direct bonding, and the dummy chip is not electrically connected to the plurality of first semiconductor chips. According to another aspect of the present disclosure, a semiconductor package includes a first substrate, a base chip disposed on the first substrate, a plurality of first semiconductor chips stacked on the base chip, a dummy chip stacked on an uppermost first semiconductor chip among the plurality of first semiconductor chips and having a channel extending from a lower surface of the dummy chip to an upper surface of the dummy chip, a first molding member surrounding the base chip, the plurality of first semiconductor chips, and the dummy chip and filling the channel, and a second molding member surrounding respective side surfaces of the first molding member and the base chip on the first substrate, wherein a semiconductor chip pad and a dielectric layer surrounding a side surface of the semiconductor chip pad are provided on each of lower surfaces and upper surfaces of the plurality of first semiconductor chips, the channel has a shape extending from a center of the dummy chip to at least any four points located at an edge of the dummy chip, in a horizontal direction in a top view, and an upper surface of the first molding member is coplanar with the upper surface of the dummy chip. BRIEF DESCRIPTION OF THE DRAWINGS Embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. FIG. 1 is a top view schematically illustrating a semiconductor package according to implementations. FIG. 2 is a cross-sectional view taken along line X1-X1' of the semiconductor package of FIG. 1. FIG. 3 is a top view schematically illustrating a semiconductor package according to implementations. FIG. 4 is a cross-sectional view taken along line X1-X1' of the semiconductor package of FIG. 3. FIG. 5 is a top view schematically illustrating a semiconductor package according to implementations. FIG. 6 is a cross-sectional view taken along line X1-X1' of the semiconductor package of FIG. 5. FIG. 7 is a top view schematically illustrating a semiconductor package according