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US-20260130222-A1 - REDUCED WARPAGE ELECTRONIC PACKAGE AND PACKAGING STRUCTURE

US20260130222A1US 20260130222 A1US20260130222 A1US 20260130222A1US-20260130222-A1

Abstract

An electronic package is provided which includes a continuous stiffener element (i.e., frame) located around a semiconductor die. The continuous stiffener element has a coefficient of thermal expansion (CTE) that closely matches the CTE of a carrier substrate that is located beneath the semiconductor die. The closely matched CTA between the continuous stiffener element and the carrier substrate reduced warpage in an electronic package containing the same. A molding component can be disposed between the continuous stiffener element and the semiconductor die. The electronic package having the reduced warpage can be used as a component of an electronic packaging structure.

Inventors

  • Katsuyuki Sakuma
  • QIANWEN CHEN
  • Sathyanarayanan Raghavan
  • John Lucas Darling
  • Roy R. Yu

Assignees

  • INTERNATIONAL BUSINESS MACHINES CORPORATION

Dates

Publication Date
20260507
Application Date
20241107

Claims (19)

  1. 1 . An electronic package comprising: a continuous stiffener element located around an entire perimeter of a semiconductor die; a molding component located between, and beneath, the continuous stiffener element and the semiconductor die; and a carrier substrate attached to the continuous stiffener element and the semiconductor die, wherein the continuous stiffener element is composed of a stiffener material having a coefficient of thermal expansion (CTE) that closely matches a CTE of the carrier substrate.
  2. 2 . The electronic package of claim 1 , wherein the carrier substrate is spaced apart from the semiconductor die and the continuous stiffener element by the molding component.
  3. 3 . The electronic package of claim 1 , wherein the stiffener material comprises a semiconductor material, a carbide, a ceramic, a metal, SiN, AlN, diamond-like carbon or any combination or multilayered stack thereof.
  4. 4 . The electronic package of claim 1 , wherein the stiffener material has a Young's modulus that closely matches a Young's modulus of the carrier substrate.
  5. 5 . The electronic package of claim 1 , wherein the molding component comprises a filler, and the filler has a CTE that closely matches the CTE of both the stiffener material and the carrier substrate.
  6. 6 . The electronic package of claim 1 , wherein the stiffener material and the carrier substrate both include silicon.
  7. 7 . The electronic package of claim 1 , wherein the carrier substrate is attached to the continuous stiffener element and the semiconductor die by at least one first bonding element.
  8. 8 . The electronic package of claim 1 , wherein the carrier substrate comprises an interposer structure, and the interposer structure comprises electrically conductive wiring and at least one electrically conductive through via structure.
  9. 9 . The electronic package of claim 1 , wherein the molding component is composed of a composite material that comprises a molding resin and a filler.
  10. 10 . An electronic package comprising: a plurality of semiconductor die attached to a carrier substrate, wherein each semiconductor die of the plurality of semiconductor die is surrounded by a continuous stiffener element, in which the continuous stiffener element is composed of a stiffener material having a coefficient of CTE that closely matches a CTE of the carrier substrate, and a molding component located between, and beneath, the continuous stiffener element and each semiconductor die.
  11. 11 . An electronic packaging structure comprising: a 0 th level package comprising a continuous stiffener element located around an entire perimeter of a semiconductor die, a molding component located between and beneath the continuous stiffener element and the semiconductor die, and a carrier substrate attached to the continuous stiffener element and the semiconductor die, wherein the continuous stiffener element is composed of a stiffener material having a coefficient of thermal expansion (CTE) that closely matches a CTE of the carrier substrate; a first level stiffener element located adjacent to the 0 th level package; a first level molding component located between the 0 th level package and the first level stiffener element, and beneath the first level stiffener element; and a first laminate attached to the carrier substrate and in contact with the first level molding component.
  12. 12 . The electronic packaging structure of claim 11 , further comprises a second laminate attached to the first laminate.
  13. 13 . The electronic packaging structure of claim 11 , wherein the stiffener material of the continuous stiffener element has a Young's modulus that closely matches a Young's modulus of the carrier substrate.
  14. 14 . The electronic packaging structure of claim 11 , wherein the molding component comprises a filler, and the filler has a CTE that closely matches the CTE of both the stiffener material of the continuous stiffener element and the carrier substrate.
  15. 15 . The electronic packaging structure of claim 11 , wherein the stiffener material of the continuous stiffener element and the carrier substrate both comprise silicon.
  16. 16 . The electronic packaging structure of claim 11 , wherein the molding component is composed of a composite material that comprises a molding resin and a filler.
  17. 17 . The electronic package structure of claim 11 , wherein the first level stiffener element is composed of a stiffener material having a CTE that closely matches a CTE of the first laminate.
  18. 18 . The electronic packaging structure of claim 11 , wherein the first level stiffener element is composed of a stiffener material having a Young's modulus that closely matches a Young's modulus the first laminate.
  19. 19 . The electronic packaging structure of claim 11 , wherein the first level stiffener element is a continuous stiffener element.

Description

BACKGROUND The present application relates to semiconductor technology, and more particularly to an electronic package, i.e., a zero (0th) level package, having reduced warpage, and an electronic packaging structure that includes the reduced warpage electronic package. Warpage is one concern in advanced packaging, such as, for example, die-to-Si carrier chiplets, where a heterogeneous mix of materials can cause uneven stress points during assembly and packaging, and under real workloads in the field. Warpage can play a critical role in determining whether an advanced package can be assembled successfully and meet long-term reliability targets. New advances, such as molding compounds with improved thermal properties, advanced modeling techniques, and creative architectures involving two molding steps have been used to enable greater control over package warpage, while also providing more flexibility to optimize a robust multi-chip (i.e., die) system. Warpage is the inevitable result of the mismatch in coefficients of thermal expansion (CTEs) and modulus between the silicon chip, molding compound, copper wiring, and other materials. Warpage can change throughout the assembly process, and can cause cracking or delamination failures. Even when warpage is effectively addressed during assembly and packaging, a device still may warp under heavy usage in the field. This is particularly the case in heterogeneous designs, where chips (or die) are developed using different materials or processes. SUMMARY An electronic package, which can be used as a component of an electronic packaging structure, is provided that includes a continuous stiffener element (i.e., frame) located around a semiconductor die. The continuous stiffener element has a CTE that closely matches the CTE of a carrier substrate that is located beneath the semiconductor die. A molding component can be disposed between, and beneath, the continuous stiffener element and the semiconductor die. In one embodiment of the present application, an electronic package is provided that includes a continuous stiffener element located around an entire perimeter of a semiconductor die, a molding component located between, and beneath, the continuous stiffener element and the semiconductor die, and a carrier substrate attached to the continuous stiffener element and the semiconductor die. In accordance with the present application, the continuous stiffener element is composed of a stiffener material having a CTE that closely matches a CTE of the carrier substrate. The electronic package can be in die form or in wafer form. The electronic package can be a 0th level package within an electronic packaging structure. In another embodiment of the present application, an electronic package is provided that includes a plurality of semiconductor die attached to a carrier substrate. Each semiconductor die of the plurality of semiconductor die is surrounded by a continuous stiffener element, in which the continuous stiffener element is composed of a stiffener material having a CTE that closely matches a CTE of the carrier substrate. The electronic package also includes a molding component located between, and beneath, the continuous stiffener element and each semiconductor die. The electronic package can be in die form or in wafer form. The electronic package can be a 0th level package within an electronic packaging structure. In yet another embodiment, an electronic packaging structure is provided that includes a 0th level package including a continuous stiffener element located around an entire perimeter of a semiconductor die, a molding component located between, and beneath, the continuous stiffener element and the semiconductor die, and a carrier substrate attached to the continuous stiffener element and the semiconductor die, in which the continuous stiffener element is composed of a stiffener material having a CTE that closely matches a CTE of the carrier substrate. The electronic packaging structure further includes a first level stiffener element located adjacent to the 0th level package, a first level molding component located between the 0th level package and the first level stiffener element, and beneath the first level stiffener element, and a first laminate attached to the carrier substrate and in contact with the first level molding component. As used throughout the present application, the term “closely matches” when referred to a CTE between a first material and a second material denotes that the CTE of the first material is typically within 10% to 20% of the CTE of the second material. In some embodiments, the CTE of the first material is within 10%, 5% or even 1 % of the CTE of the second material. In some embodiments, the CTE of the first material can equal the CTE of the second material. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a top down view of an electronic package (i.e., 0th level package) in accordance with an embodiment of the present application.