US-20260130224-A1 - INTEGRATED CIRCUIT PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

Abstract

An integrated circuit package structure includes a first substrate and a second substrate. The first substrate includes a sensor and a metal routing connecting to the sensor. The second substrate is bonded to the first substrate and includes a circuit layer and a plurality of conductive connectors connecting to the circuit layer. At least one of the first substrate and the second substrate further includes a stacked metal structure configured to provide electrostatic discharge protection.

Inventors

• Bo-Yu Chiu
• Hong-Seng Shue
• Steven Sze Hang Poon
• Chih-Yu Chou
• Wei-Chao Chang

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date

20260507

Application Date

20241105

Claims (20)

1. 1 . An integrated circuit package structure, comprising: a first substrate comprising a sensor and a metal routing connecting to the sensor; and a second substrate bonded to the first substrate and comprising a circuit layer and a plurality of conductive connectors connecting to the circuit layer, wherein at least one of the first substrate and the second substrate further comprises a stacked metal structure configured to provide electrostatic discharge protection.
2. 2 . The integrated circuit package structure of claim 1 , wherein the first substrate comprises the stacked metal structure connecting to the sensor via the metal routing.
3. 3 . The integrated circuit package structure of claim 2 , wherein an area of the stacked metal structure is greater than 3×10 4 μm 2 .
4. 4 . The integrated circuit package structure of claim 2 , wherein a volume of the stacked metal structure is between 1.5×10 4 μm 3 and 7.5×10 4 μm 3 .
5. 5 . The integrated circuit package structure of claim 2 , wherein the stacked metal structure comprises a plurality of metal layers and a plurality of metal vias connecting the plurality of metal layers, and a via density of each layer of the plurality of metal vias is greater than 0.01%.
6. 6 . The integrated circuit package structure of claim 1 , wherein the second substrate comprises the stacked metal structure disposed around the circuit layer, and a metal area of the stacked metal structure is greater than or equal to 2× 10 6 μm 2 .
7. 7 . An integrated circuit package structure, comprising: a first substrate comprising a sensor, a metal routing, a stacked metal structure and a capacitor structure, wherein the metal routing connects the sensor and the stacked metal structure, and the capacitor structure is connected to the stacked metal structure, wherein the stacked metal structure and the capacitor structure are configured to provide electrostatic discharge protection; and a second substrate bonded to the first substrate and comprising a circuit layer and a plurality of conductive connectors connecting to the circuit layer.
8. 8 . The integrated circuit package structure of claim 7 , wherein a width of the capacitor structure is between 50 μm and 350 μm.
9. 9 . The integrated circuit package structure of claim 7 , wherein the capacitor structure comprises a plurality of dielectric layers and a plurality of conductive vias penetrating through the plurality of dielectric layers.
10. 10 . The integrated circuit package structure of claim 9 , wherein a permittivity of the plurality of dielectric layers is greater than 10.
11. 11 . The integrated circuit package structure of claim 9 , wherein each of the plurality of dielectric layers has an opening, and a diameter of the opening is between 1 μm and 10 μm.
12. 12 . The integrated circuit package structure of claim 9 , wherein a via density of the plurality of conductive vias is between 0.1% and 10%.
13. 13 . The integrated circuit package structure of claim 9 , wherein a width of each of the plurality of conductive vias is between 1 μm and 10 μm.
14. 14 . The integrated circuit package structure of claim 7 , wherein an area of the stacked metal structure is greater than 3×10 4 μm 2 .
15. 15 . The integrated circuit package structure of claim 7 , wherein a volume of the stacked metal structure is between 1.5×10 4 μm 3 and 7.5×10 4 μm 3 .
16. 16 . The integrated circuit package structure of claim 7 , wherein the stacked metal structure comprises a plurality of metal layers and a plurality of metal vias connecting the plurality of metal layers, and a via density of each layer of the plurality of metal vias is greater than 0.01%.
17. 17 . A manufacturing method of an integrated circuit package structure, comprising: providing a first substrate comprising a sensor, a metal routing, a first stacked metal structure and a capacitor structure, wherein the metal routing connects the sensor and the first stacked metal structure, and the capacitor structure is connected to the first stacked metal structure; and bonding a second substrate to the first substrate, the second substrate comprising a circuit layer, a plurality of first conductive connectors connecting to the circuit layer and a second stacked metal structure disposed around the circuit layer, wherein the first stacked metal structure, the capacitor structure and the second stacked metal structure are configured to provide electrostatic discharge protection.
18. 18 . The manufacturing method of the integrated circuit package structure of claim 17 , wherein the first substrate further comprises a plurality of first bumps, the second substrate further comprises a plurality of second bumps, and the plurality of second bumps connect to the plurality of first bumps to electrically connect the second substrate to the first substrate.
19. 19 . The manufacturing method of the integrated circuit package structure of claim 18 , further comprising: providing an underfill between the first substrate and the second substrate to cover the plurality of first bumps and the plurality of second bumps.
20. 20 . The manufacturing method of the integrated circuit package structure of claim 17 , wherein the second substrate further comprises a plurality of second conductive connectors connecting to the second stacked metal structure, and a number of the plurality of second conductive connectors is greater than or equal to 4.

Description

BACKGROUND Extremely high voltages can develop in the vicinity of integrated circuits due to the build-up of static charges. A high potential may be generated to an input buffer or an output buffer of an integrated circuit. The high potential may be caused by a person touching a package pin that is in electrical contact with the input or the output buffer. When the electrostatic charges are discharged, a high current is produced at the package nodes of the integrated circuit. This phenomenon is referred to as electrostatic discharge. The electrostatic discharge is a serious problem for semiconductor devices since it can potentially destroy the entire integrated circuit. The duration of the electrostatic discharge transient is very short, typically in the order of nanoseconds, and the conventional circuit breakers cannot react quickly enough to provide adequate protection. For this reason, it has become a known practice to incorporate electrostatic discharge devices in integrated circuits. Conventionally, bi-directional diode strings were coupled between the package pins to protect the respective circuit. Other electrostatic discharge devices such as transistors were also used. The electrostatic discharge devices were also widely used between power lines to protect the internal circuits coupled between the power lines and to discharge electrostatic discharge currents to the ground. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1A is schematic view illustrating an integrated circuit package structure in accordance with some embodiments of the disclosure. FIG. 1B is a schematic cross-sectional view illustrating the integrated circuit package structure of FIG. 1A. FIG. 1C is a schematic enlarged partial view illustrating the integrated circuit package structure of FIG. 1B. FIG. 2 is a schematic cross-sectional view illustrating an integrated circuit package structure in accordance with some alternative embodiments of the disclosure. FIG. 3 is a schematic cross-sectional view illustrating an integrated circuit package structure in accordance with some alternative embodiments of the disclosure. FIG. 4 is a schematic cross-sectional view illustrating an integrated circuit package structure in accordance with some alternative embodiments of the disclosure. FIG. 5 is a schematic cross-sectional view illustrating an integrated circuit package structure in accordance with some alternative embodiments of the disclosure. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction w