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US-20260130225-A1 - SEMICONDUCTOR PACKAGE AND PACKAGE-ON-PACKAGE HAVING DIFFERENT WIRING INSULATING LAYERS SURROUNDING DIFFERENTIAL SIGNAL WIRING LAYERS

US20260130225A1US 20260130225 A1US20260130225 A1US 20260130225A1US-20260130225-A1

Abstract

A semiconductor includes: a lower equipotential plate provided in a lower wiring layer; an upper equipotential plate provided in an upper wiring layer; a pair of differential signal wiring lines provided in a signal wiring layer that is between the lower equipotential plate and the upper equipotential plate, wherein the pair of differential signal wiring lines includes a first differential signal wiring line and a second differential signal wiring line which are spaced apart from each other and extend in parallel; and a wiring insulating layer surrounding the pair of differential signal wiring lines, and filling between the signal wiring layer, the lower wiring layer, and the upper wiring layer. The wiring insulating layer includes a first wiring insulating layer surrounding the pair of differential signal wiring lines, and a second wiring insulating layer, and the first wiring insulating layer and the second wiring insulating layer include different materials.

Inventors

  • Juyoun CHOI
  • Seongho Shin

Assignees

  • SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date
20260507
Application Date
20251222
Priority Date
20220329

Claims (20)

  1. 1 . A substrate comprising: a pair of differential signal wiring lines provided in a signal wiring layer comprises a first differential signal wiring line and a second differential signal wiring line which are spaced apart from each other along a first horizontal direction and extend in parallel along a second horizontal direction which crosses the first horizontal direction; and a wiring insulating layer surrounding the pair of differential signal wiring lines, wherein the wiring insulating layer comprises a first wiring insulating layer surrounding the pair of differential signal wiring lines, and a second wiring insulating layer surrounding the first wiring insulating layer, and wherein the first wiring insulating layer and the second wiring insulating layer comprise different materials.
  2. 2 . The substrate of claim 1 , wherein the pair of differential signal wiring lines and the second wiring insulating layer are spaced apart from each other by the first wiring insulating layer.
  3. 3 . The substrate of claim 1 , wherein an upper surface of the first wiring insulating layer and an upper surface of the second wiring insulating layer are located at different vertical levels.
  4. 4 . The substrate of claim 1 , wherein an upper surface of the first wiring insulating layer is in contact with the second wiring insulating layer.
  5. 5 . The substrate of claim 1 , wherein the pair of differential signal wiring lines is in contact with the second wiring insulating layer.
  6. 6 . The substrate of claim 1 , wherein a side surface of the first wiring insulating layer is in contact with a side surface of the second wiring insulating layer.
  7. 7 . The substrate of claim 1 , further comprising: a surrounding equipotential plate which defines a differential signal opening provided in the signal wiring layer, spaced apart from the pair of differential signal wiring lines in a horizontal direction, and surrounding the pair of differential signal wiring lines.
  8. 8 . The substrate of claim 1 , wherein a first relative dielectric constant of the first wiring insulating layer is less than a second relative dielectric constant of the second wiring insulating layer.
  9. 9 . A substrate comprising: a lower equipotential plate, an upper equipotential plate provided in an upper wiring layer, wherein the upper equipotential plate overlaps the lower equipotential plate along a vertical direction, a surrounding equipotential plate which defines a differential signal opening between the lower equipotential plate and the upper equipotential plate, a signal wiring layer inside the differential signal opening, and a lower wiring layer in which the lower equipotential plate is provided, wherein a pair of differential signal wiring lines is provided in the signal wiring layer and comprises a first differential signal wiring line and a second differential signal wiring line which extend apart from each other, a wiring insulating layer surrounding the pair of differential signal wiring lines, and filling between the signal wiring layer, the lower wiring layer, and the upper wiring layer, wherein the wiring insulating layer comprises a first wiring insulating layer surrounding the pair of differential signal wiring lines, and a second wiring insulating layer surrounding the first wiring insulating layer, and wherein the first wiring insulating layer and the second wiring insulating layer comprise different materials.
  10. 10 . The substrate of claim 9 , wherein a first thickness of the first wiring insulating layer is greater than a second thickness of the signal wiring layer, and wherein a first horizontal width of the first wiring insulating layer is greater than a second horizontal width of the pair of differential signal wiring lines.
  11. 11 . The substrate of claim 9 , further comprising: a single signal wiring line provided in the signal wiring layer and spaced apart from the pair of differential signal wiring lines, and wherein the single signal wiring line overlaps each of the lower equipotential plate and the upper equipotential plate along the vertical direction.
  12. 12 . The substrate of claim 11 , wherein the single signal wiring line is in contact with the second wiring insulating layer.
  13. 13 . The substrate of claim 9 , wherein the lower equipotential plate and the upper equipotential plate respectively define a lower impedance opening and an upper impedance opening which overlap at least a portion of the pair of differential signal wiring lines along the vertical direction.
  14. 14 . The substrate of claim 13 , wherein the first wiring insulating layer fills at least a portion of the lower impedance opening and the upper impedance opening.
  15. 15 . The substrate of claim 13 , wherein the first wiring insulating layer is spaced apart from each of the lower impedance opening and the upper impedance opening in the vertical direction.
  16. 16 . The substrate of claim 9 , wherein an upper surface of the first wiring insulating layer is in contact with a lower surface of the upper equipotential plate, or a lower surface of the first wiring insulating layer is in contact with an upper surface of the lower equipotential plate.
  17. 17 . The substrate of claim 9 , wherein the wiring insulating layer comprises a dielectric opening portion disposed adjacent to the pair of differential signal wiring lines to adjust an impedance of the pair of differential signal wiring lines.
  18. 18 . A substrate comprising: a redistribution layer comprising: a lower equipotential plate provided in a lower wiring layer, a surrounding equipotential plate which defines a differential signal opening disposed on the lower equipotential plate, a signal wiring layer inside the differential signal opening, and comprising a pair of differential signal wiring lines is provided in the signal wiring layer and comprises a first differential signal wiring line and a second differential signal wiring line which extend apart from each other, a wiring insulating layer surrounding the pair of differential signal wiring lines, and filling between the signal wiring layer and the lower wiring layer, wherein the wiring insulating layer comprises a first wiring insulating layer surrounding the pair of differential signal wiring lines, and a second wiring insulating layer surrounding the first wiring insulating layer, and wherein the first wiring insulating layer and the second wiring insulating layer comprise different materials.
  19. 19 . The substrate of claim 18 , wherein the first relative dielectric constant ranges from 0.5 to 2.5, and the second relative dielectric constant ranges from 2.5 to 5.
  20. 20 . The substrate of claim 18 , wherein a horizontal width of the first wiring insulating layer ranges from 15 μm to 500 μm, and wherein a thickness of the first wiring insulating layer ranges from 3 μm to 100 μm.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is a Continuation Application of U.S. application Ser. No. 18/075,878, filed on Dec. 6, 2022, which claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0039177, filed on Mar. 29, 2022, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety. BACKGROUND The present disclosure relates to a semiconductor package and a package-on-package having the same, and more particularly, to a fan-out semiconductor package and a package-on-package having the same. With the rapid development of the electronics industry and user demand, electronic apparatuses have become more compact and multi-functional, and increased in capacity, and accordingly, highly integrated semiconductor chips are demanded. Accordingly, semiconductor packages having connection terminals securing connection reliability have been devised for highly integrated semiconductor chips having an increased number of connection terminals for input/output (I/O). For example, to prevent interference between connection terminals, fan-out semiconductor packages in which an interval between connection terminals is increased have been developed. SUMMARY The present disclosure provides a semiconductor package with improved signal integrity and a package-on-package having the same. According to an aspect of an example embodiment, a semiconductor package includes: a lower equipotential plate provided in a lower wiring layer; an upper equipotential plate provided in an upper wiring layer; a pair of differential signal wiring lines provided in a signal wiring layer that is between the lower equipotential plate and the upper equipotential plate, wherein the pair of differential signal wiring lines includes a first differential signal wiring line and a second differential signal wiring line which are spaced apart from each other and extend in parallel; and a wiring insulating layer surrounding the pair of differential signal wiring lines, and filling between the signal wiring layer, the lower wiring layer, and the upper wiring layer. The wiring insulating layer includes a first wiring insulating layer surrounding the pair of differential signal wiring lines, and a second wiring insulating layer, and the first wiring insulating layer and the second wiring insulating layer include different materials. According to an aspect of an example embodiment, a semiconductor package includes: a lower redistribution layer including a plurality of lower redistribution line patterns, a plurality of lower redistribution via patterns, a lower equipotential plate, and a lower redistribution insulating layer, wherein the lower redistribution layer includes a signal wiring layer and a lower wiring layer under the signal wiring layer, wherein a pair of differential signal wiring lines are provided in the plurality of lower redistribution line patterns in the signal wiring layer, wherein the lower equipotential plate is provided in the lower wiring layer, and wherein the pair of differential signal wiring lines includes a first differential signal wiring line and a second differential signal wiring line which are spaced apart from each other; an expanded layer overlapping portions of the pair of differential signal wiring lines along a vertical direction on the lower redistribution layer, the expanded layer including a substrate base having a mounting space, a plurality of wiring patterns and an upper equipotential plate on a surface of the substrate base, and a plurality of conductive vias passing through at least a portion of the substrate base, wherein the expanded layer has an upper wiring layer in which the upper equipotential plate is provided; and a semiconductor chip provided on the lower redistribution layer in the mounting space. The lower redistribution layer includes a first wiring insulating layer surrounding the pair of differential signal wiring lines, and a second wiring insulating layer. The pair of differential signal wiring lines and the second wiring insulating layer are spaced apart from each other. A first relative dielectric constant of the first wiring insulating layer is less than a second relative dielectric constant of the second wiring insulating layer. According to an aspect of an example embodiment, a semiconductor package includes: a first semiconductor package including a lower redistribution layer, an expanded layer, a first semiconductor chip, and an upper redistribution layer, the lower redistribution layer including a surrounding equipotential plate which defines a differential signal opening, a signal wiring layer inside the differential signal opening, and a lower wiring layer in which a lower equipotential plate is provided, wherein a pair of differential signal wiring lines is provided in the signal wiring layer and includes a first differential signal wiring line and a second differential signal wiring line wh