US-20260130226-A1 - SEMICONDUCTOR DEVICE

US20260130226A1US 20260130226 A1US20260130226 A1US 20260130226A1US-20260130226-A1

Abstract

A semiconductor device includes an insulating substrate, a plurality of semiconductor elements, a gate terminal, a printed circuit board and a passive component. The insulating substrate has a wiring. Each of the plurality of semiconductor elements has a first main electrode disposed on a first surface, a second main electrode disposed on a second surface opposite to the first surface, and a gate pad disposed on the second surface. The first main electrodes of the plurality of semiconductor elements are commonly connected to the wiring. The printed circuit board provides a gate wiring that electrically relays the gate pad and the gate terminal. The passive component includes a ferrite bead or a balance resistor. The passive component is mounted on the printed circuit board to adjust an impedance of the gate wiring.

Inventors

Yuri Imai
Masayoshi Nishihata
Chihiro Kato

Assignees

DENSO CORPORATION

Dates

Publication Date: 20260507
Application Date: 20260102
Priority Date: 20230705

Claims (3)

1 . A semiconductor device comprising: an insulating substrate having a wiring; a plurality of semiconductor elements each having a first main electrode disposed on a first surface, a second main electrode disposed on a second surface opposite to the first surface, and a gate pad disposed on the second surface, the first main electrodes of the plurality of semiconductor elements being commonly connected to the wiring; a gate terminal; a printed circuit board providing a gate wiring that electrically relays the gate pad and the gate terminal; and a passive component including a ferrite bead or a balance resistor, the passive component mounted on the printed circuit board to adjust an impedance of the gate wiring, wherein the insulating substrate includes an insulating base material containing ceramic, and the printed circuit board includes an insulating base material containing a resin.
2 . The semiconductor device according to claim 1 , wherein the printed circuit board is mounted on the insulating substrate.
3 . The semiconductor device according to claim 1 , further comprising: a metal member joined to the second main electrodes of the plurality of semiconductor elements, wherein the printed circuit board is disposed on the metal member.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS The present application is a continuation application of International Patent Application No. PCT/JP2024/020601 filed on Jun. 6, 2024, which designated the U.S. and claims the benefit of priority from Japanese Patent Application No. 2023-110773 filed on Jul. 5, 2023. The entire disclosures of all of the above applications are incorporated herein by reference. TECHNICAL FIELD The present disclosure herein relates to a semiconductor device. BACKGROUND JP 2002-153079 A discloses a semiconductor device. Contents of the description of JP 2002-153079 A are incorporated herein by reference as a description of technical elements in this description. SUMMARY According to an aspect of the present disclosure, a semiconductor device may include an insulating substrate, a plurality of semiconductor elements, a gate terminal, a printed circuit board and a passive component. The insulating substrate may have a wiring. Each of the plurality of semiconductor elements may have a first main electrode on a first surface, a second main electrode on a second surface opposite to the first surface, and a gate pad on the second surface. The first main electrodes of the plurality of semiconductor elements may be commonly connected to the wiring. The printed circuit board may provide a gate wiring that electrically relays the gate pad and the gate terminal. The passive component may include a ferrite bead or a balance resistor. The passive component may be mounted on the printed circuit board to adjust an impedance of the gate wiring. BRIEF DESCRIPTION OF DRAWINGS Features and advantages of the present disclosure will become more apparent from the following detailed description made with reference to the accompanying drawings. FIG. 1 is a diagram illustrating a circuit configuration of a power conversion device to which a semiconductor device according to a first embodiment is applied. FIG. 2 is a perspective view illustrating an example of a semiconductor module. FIG. 3 is a plan view of the semiconductor module. FIG. 4 is a cross-sectional view taken along a line IV-IV in FIG. 3. FIG. 5 is a plan view illustrating an example of the semiconductor device. FIG. 6 is a plan view illustrating a wiring pattern of a substrate. FIG. 7 is a cross-sectional view taken along a line VII-VII in FIG. 5. FIG. 8 is a cross-sectional view illustrating another example of the connection structure between a capacitor and the substrate. FIG. 9 is a cross-sectional view illustrating still another example of the connection structure between the capacitor and the substrate. FIG. 10 is a cross-sectional view illustrating still another example of the connection structure between the capacitor and the substrate. FIG. 11 is a circuit diagram illustrating a verification model. FIG. 12 is a diagram illustrating a verification result. FIG. 13 is a diagram illustrating a temperature distribution. FIG. 14 is a diagram illustrating disposition of a current path formed by a snubber circuit. FIG. 15 is a plan view illustrating a modification example. FIG. 16 is a plan view illustrating another modification example. FIG. 17 is a plan view illustrating still another modification example. FIG. 18 is a plan view illustrating a semiconductor element in a semiconductor device according to a second embodiment. FIG. 19 is a cross-sectional view taken along a line XIX-XIX in FIG. 18. FIG. 20 is a partial cross-sectional view of the semiconductor device and a semiconductor module. FIG. 21 is a plan view illustrating an example of a connection structure between a clip and the semiconductor element. FIG. 22 is a cross-sectional view taken along a line XXII-XXII in FIG. 21. FIG. 23 is a plan view illustrating another example of the connection structure between the clip and the semiconductor element. FIG. 24 is a perspective view illustrating the clip. FIG. 25 is a plan view illustrating another example of the clip. FIG. 26 is a plan view illustrating still another example of the clip. FIG. 27 is a cross-sectional view illustrating still another example of the clip. FIG. 28 is a plan view illustrating still another example of the clip. FIG. 29 is a plan view illustrating still another example of the connection structure between the clip and the semiconductor element. FIG. 30 is a cross-sectional view taken along a line XXX-XXX in FIG. 29. FIG. 31 is a plan view illustrating still another example of the clip. FIG. 32 is a plan view illustrating still another example of the clip. FIG. 33 is a plan view illustrating still another example of the clip. FIG. 34 is a plan view illustrating still another example of the clip. FIG. 35 is a plan view illustrating still another example of the clip. FIG. 36 is a plan view illustrating still another example of the clip. FIG. 37 is a plan view illustrating still another example of the clip. FIG. 38 is a plan view illustrating still another example of the clip. FIG. 39 is a plan view illustrating still anot