US-20260130227-A1 - SEMICONDUCTOR DEVICE

US20260130227A1US 20260130227 A1US20260130227 A1US 20260130227A1US-20260130227-A1

Abstract

A semiconductor device includes a substrate, a plurality of semiconductor elements, and a main terminal. Each of the plurality of semiconductor elements has a main electrode. The plurality of semiconductor elements are disposed on one surface of the substrate, and are connected in parallel to each other. The main terminal is a common connection target to which the plurality of semiconductor elements are electrically connected. A wiring resistance between the main terminal and the main electrode of a corresponding semiconductor element is different in accordance with a number of semiconductor elements disposed adjacent to the corresponding semiconductor element, and the wiring resistance increases as the number of the semiconductor elements disposed adjacent to the corresponding semiconductor element increases.

Inventors

Keita HATASA
Masayoshi Nishihata
Takahiro Hirano
Yuri Imai

Assignees

DENSO CORPORATION

Dates

Publication Date: 20260507
Application Date: 20260102
Priority Date: 20230705

Claims (13)

1 . A semiconductor device comprising: a substrate having one surface; a plurality of semiconductor elements each having a main electrode, the plurality of semiconductor elements disposed on the one surface of the substrate and connected in parallel to each other; and a main terminal as a common connection target to which the plurality of semiconductor elements are electrically connected, wherein a wiring resistance between the main terminal and the main electrode of a corresponding semiconductor element is different in accordance with a number of semiconductor elements disposed adjacent to the corresponding semiconductor element, and the wiring resistance increases as the number of the semiconductor elements disposed adjacent to the corresponding semiconductor element increases.
2 . The semiconductor device according to claim 1 , wherein the substrate includes a common wiring disposed on the one surface and to which the main terminal is joined and the main electrodes of the plurality of semiconductor elements are commonly connected, and the common wiring is arranged so that a length from a joint portion of the common wiring to the main terminal to an electrical connection portion of the main electrode of the corresponding semiconductor element increases as the number of the semiconductor elements disposed adjacent to the corresponding semiconductor element increases.
3 . The semiconductor device according to claim 2 , wherein the plurality of semiconductor elements are a plurality of first semiconductor elements, the semiconductor device further comprising: a plurality of second semiconductor elements disposed on the one surface of the substrate and connected in parallel to each other, wherein one of the plurality of first semiconductor elements or the plurality of second semiconductor elements provides an upper arm of an upper and lower arm circuit, and an other of the plurality of first semiconductor elements or the plurality of second semiconductor elements provides a lower arm of the upper and lower arm circuit, the plurality of first semiconductor elements are aligned in a first direction, the plurality of second semiconductor elements are aligned in the first direction, the plurality of second semiconductor elements are disposed between the main terminal and the plurality of first semiconductor elements in a second direction orthogonal to the first direction, and the common wiring is arranged to bypass the plurality of second semiconductor elements.
4 . The semiconductor device according to claim 3 , wherein the plurality of second semiconductor elements are provided in a same number as the plurality of first semiconductor elements, a position of the first semiconductor element in which current flows more easily than in the other of the first semiconductor elements is offset from a position of the second semiconductor element in which current flows more easily than in the other of the second semiconductor elements in the first direction.
5 . The semiconductor device according to claim 3 , wherein the plurality of first semiconductor elements provide the lower arm.
6 . The semiconductor device according to claim 1 , wherein a temperature of only one of the plurality of semiconductor elements is output.
7 . A semiconductor device comprising: a substrate having a wiring on one surface; a plurality of semiconductor elements each having a main electrode, the plurality of semiconductor elements disposed on the one surface of the substrate and connected in parallel to each other; a main terminal as a common connection target to which the main electrodes of the plurality of semiconductor elements are commonly connected; and a metal plate that electrically connects at least two of the plurality of semiconductor elements, the at least two of the plurality of semiconductor elements having at least one of (i) different numbers of adjacent semiconductor elements or (ii) different current path lengths between the main electrodes thereof and the main terminal.
8 . The semiconductor device according to claim 7 , wherein a temperature of only one of the plurality of semiconductor elements is output.
9 . A semiconductor device comprising: a substrate having a conductor on one surface; and a plurality of semiconductor elements disposed on the one surface of the substrate, wherein the plurality of semiconductor elements includes an upper arm element that provides an upper arm of an upper and lower arm circuit and a lower arm element that provides a lower arm of the upper and lower arm circuit, the conductor includes a first conductor on which the plurality of semiconductor elements are mounted and a second conductor that is separated from the first conductor and on which the plurality of semiconductor elements are not mounted, the first conductor includes a first portion on which the upper arm element is mounted and a second portion on which the lower arm element is mounted, the first portion and the second portion have different areas in a plan view in a thickness direction of the substrate, and the second conductor is disposed closer to a smaller one of the first portion and the second portion than the other.
10 . The semiconductor device according to claim 9 , further comprising: a snubber circuit including a capacitor and disposed on the one surface of the substrate, wherein the capacitor is disposed on the second conductor.
11 . The semiconductor device according to claim 9 , wherein the first conductor is made of a highly thermal-conductive material having a higher thermal conductivity than a material of an other part of the conductor including the second conductor.
12 . The semiconductor device according to claim 11 , wherein the plurality of semiconductor elements includes a plurality of the upper arm elements aligned in a predetermined direction perpendicular to the thickness direction, and a plurality of the lower arm elements aligned in the predetermined direction, and the highly thermal-conductive material has anisotropy, and a direction of the higher thermal conductivity coincides with the predetermined direction.
13 . The semiconductor device according to claim 9 , wherein a temperature of only one of the plurality of semiconductor elements is output.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS The present application is a continuation application of International Patent Application No. PCT/JP2024/020599 filed on June 6, 2024, which designated the U.S. and claims the benefit of priority from Japanese Patent Application No. 2023-110771 filed on July 5, 2023. The entire disclosures of all of the above applications are incorporated herein by reference. TECHNICAL FIELD The present disclosure herein relates to a semiconductor device. BACKGROUND JP 2002-368192 A discloses a semiconductor device. Contents of the description of JP 2002-368192 A are incorporated herein by reference as a description of technical elements in this description. SUMMARY According to an aspect of the present disclosure, a semiconductor device includes a substrate, a plurality of semiconductor elements and a main terminal. Each of the plurality of semiconductor elements has a main electrode. The plurality of semiconductor elements are disposed on one surface of the substrate and connected in parallel to each other. The main terminal is provided as a common connection target to which the plurality of semiconductor elements are electrically connected. A wiring resistance between the main terminal and the main electrode of a corresponding semiconductor element is different in accordance with a number of semiconductor elements disposed adjacent to the corresponding semiconductor element, and the wiring resistance increases as the number of the semiconductor elements disposed adjacent to the corresponding semiconductor element increases. BRIEF DESCRIPTION OF DRAWINGS Features and advantages of the present disclosure will become more apparent from the following detailed description made with reference to the accompanying drawings. FIG. 1 is a diagram illustrating a circuit configuration of a power conversion device to which a semiconductor device according to a first embodiment is applied. FIG. 2 is a perspective view illustrating an example of a semiconductor module. FIG. 3 is a plan view of the semiconductor module. FIG. 4 is a cross-sectional view taken along a line IV-IV in FIG. 3. FIG. 5 is a plan view illustrating an example of the semiconductor device. FIG. 6 is a plan view illustrating a wiring pattern of a substrate. FIG. 7 is a cross-sectional view taken along a line VII-VII in FIG. 5. FIG. 8 is a cross-sectional view illustrating another example of the connection structure between a capacitor and the substrate. FIG. 9 is a cross-sectional view illustrating still another example of the connection structure between the capacitor and the substrate. FIG. 10 is a cross-sectional view illustrating still another example of the connection structure between the capacitor and the substrate. FIG. 11 is a circuit diagram illustrating a verification model. FIG. 12 is a diagram illustrating a verification result. FIG. 13 is a diagram illustrating a temperature distribution. FIG. 14 is a diagram illustrating disposition of a current path formed by a snubber circuit. FIG. 15 is a plan view illustrating a modification example. FIG. 16 is a plan view illustrating another modification example. FIG. 17 is a plan view illustrating still another modification example. FIG. 18 is a plan view illustrating a semiconductor element in a semiconductor device according to a second embodiment. FIG. 19 is a cross-sectional view taken along a line XIX-XIX in FIG. 18. FIG. 20 is a partial cross-sectional view of the semiconductor device and a semiconductor module. FIG. 21 is a plan view illustrating an example of a connection structure between a clip and the semiconductor element. FIG. 22 is a cross-sectional view taken along a line XXII-XXII in FIG. 21. FIG. 23 is a plan view illustrating another example of the connection structure between the clip and the semiconductor element. FIG. 24 is a perspective view illustrating the clip. FIG. 25 is a plan view illustrating another example of the clip. FIG. 26 is a plan view illustrating still another example of the clip. FIG. 27 is a cross-sectional view illustrating still another example of the clip. FIG. 28 is a plan view illustrating still another example of the clip. FIG. 29 is a plan view illustrating still another example of the connection structure between the clip and the semiconductor element. FIG. 30 is a cross-sectional view taken along a line XXX-XXX in FIG. 29. FIG. 31 is a plan view illustrating still another example of the clip. FIG. 32 is a plan view illustrating still another example of the clip. FIG. 33 is a plan view illustrating still another example of the clip. FIG. 34 is a plan view illustrating still another example of the clip. FIG. 35 is a plan view illustrating still another example of the clip. FIG. 36 is a plan view illustrating still another example of the clip. FIG. 37 is a plan view illustrating still another example of the clip. FIG. 38 is a plan view illustrating still another example of the clip. FIG. 39 is a plan view illustrating still an