US-20260130229-A1 - Memory Circuitry And Methods Used In Forming Memory Circuitry

Abstract

Memory circuitry comprises an integrated circuit die comprising a radially-outermost region surrounding a radially-inner region. The inner region comprises a memory-array region. The radially-outermost region comprises a lower semiconductor material, insulative material directly above the lower semiconductor material, and a stack comprising alternating tiers of different composition semiconductive materials directly above the insulative material. A conductive-wall construction is in the radially-outermost region at least partially surrounding the inner region. Other embodiments, including methods, are disclosed.

Inventors

• Pavani Vamsi Krishna NITTALA
• Yuichi Yokoyama
• Brenda Li
• Muralikrishnan Balakrishnan
• Kolya Yastrebenetsky

Assignees

• MICRON TECHNOLOGY, INC.

Dates

Publication Date

20260507

Application Date

20250910

Claims (20)

1. 1 .: A method used in forming memory circuitry, comprising: fabricating a semiconductor wafer to have die areas to comprise memory cells and to have scribe-line area around individual of the die areas, the scribe-line area comprising: a lower semiconductor material; an insulative material directly above the lower semiconductor material; and a stack comprising alternating tiers of different composition semiconductive materials directly above the insulative material; forming a plurality of trenches in the scribe-line area that individually at least partially surround the individual die areas, the trenches extending through the stack and the insulative material to the lower semiconductor material; and forming a conductive-wall construction in individual of the trenches and that at least partially surrounds one of the individual die areas, the conductive-wall construction extending through the stack and the insulative material to the lower semiconductor material, the conductive-wall construction comprising two laterally-outer regions of insulating material having a conductive core laterally there-between, the conductive core being directly electrically coupled to the lower semiconductor material.
2. 2 .: The method of claim 1 further comprising, through the scribe-line area, dicing the semiconductor wafer into individual die that comprise one of the die areas, the individual die comprising a radially-outermost region surrounding the one die area and that comprises part of the scribe-line area of the former semiconductor wafer, the conductive-wall construction remaining in the radially-outermost region after the dicing.
3. 3 .: The method of claim 1 wherein the conductive-wall construction completely surrounds the ones of the individual die areas.
4. 4 .: The method of claim 1 comprising forming the die areas to individually comprise a vertical stack of the memory cells, the memory cells individually comprising a capacitor and a horizontal transistor.
5. 5 .: The method of claim 1 wherein one of the different composition semiconductive materials comprises silicon and the other comprises a silicon-germanium alloy.
6. 6 .: The method of claim 1 wherein the lower semiconductor material comprises silicon.
7. 7 .: The method of claim 1 wherein the insulative material comprises silicon dioxide.
8. 8 .: The method of claim 1 wherein, the memory cells are vertically stacked and individually comprise a capacitor and a horizontal transistor; one of the different composition semiconductive materials comprises silicon and the other comprises a silicon-germanium alloy; the lower semiconductor material comprises silicon; and the insulative material comprises silicon dioxide.
9. 9 .: The method of claim 1 wherein forming the trenches sequentially comprises: initially forming the trenches to stop atop or in the insulative material; lining sidewalls of the initially-formed trenches with the insulating material; and within the initially-formed trenches, etching through the insulative material to the lower semiconductor material.
10. 10 .: The method of claim 9 comprising etching into the lower semiconductor material through the initially-formed trenches after etching through the insulative material.
11. 11 .: The method of claim 1 comprising forming more than one of said trenches and more than one of said conductive-wall construction around the individual die areas.
12. 12 .: The method of claim 11 wherein, through the scribe-line area, dicing the semiconductor wafer into individual die that comprise one of the die areas, the individual die comprising a radially-outermost region surrounding the one die area and that comprises part of the scribe-line area of the former semiconductor wafer, at least two of the conductive-wall constructions remaining in the radially-outermost region after the dicing.
13. 13 .: The method of claim 12 wherein the conductive cores of the at least two conductive-wall constructions are directly against one another in the lower semiconductor material.
14. 14 .: A method used in forming memory circuitry, comprising: fabricating a semiconductor wafer to have die areas to comprise memory cells and to have scribe-line area around individual of the die areas; forming a plurality of trenches in the scribe-line area that individually at least partially surround the individual die areas; forming the die areas to individually comprise a memory-array region and an adjacent region that is horizontally adjacent the memory-array region, the memory-array region comprising vertically-alternating insulative tiers and memory-cell tiers, the memory-cell tiers comprising memory cells that individually comprise a horizontal transistor comprising a gate, the gate comprising part of one of a plurality of horizontal conductive access lines that individually directly electrically couple together multiple of the gates of different ones of the horizontal transistors that are in the same memory-cell tier and that extend horizontally from the memory-array region into the adjacent region, conductive-via openings in the adjacent region that individually extend to have a bottom that is in one of the memory-cell tiers comprising one of the access lines; and simultaneously forming (a) and (b), where: (a): two laterally-outer regions of insulating material and a conductive core laterally there-between of a conductive-wall construction in individual of the trenches, the conductive core of the conductive-wall construction being directly electrically coupled to the lower semiconductor material; and (b): a conductive core and a radially-outer insulative lining circumferentially there-about of a conductive-via construction in individual of the conductive-via openings, the conductive core of the conductive-via construction directly electrically coupling with the one access line.
15. 15 .: The method of claim 14 wherein individual of the conductive-via openings and the conductive-via construction are laterally aside the one access line.
16. 16 .: The method of claim 14 further comprising, through the scribe-line area, dicing the semiconductor wafer into individual die that comprise one of the die areas, the individual die comprising a radially-outermost region surrounding the one die area and that comprises part of the scribe-line area of the former semiconductor wafer, the conductive-wall construction remaining in the radially outermost region after the dicing.
17. 17 - 20 . (canceled)
18. 21 .: A method used in forming memory circuitry, comprising: fabricating a semiconductor wafer to have die areas and scribe-line area around individual of the die areas; in a single masking step, simultaneously forming digitline trenches in the individual die areas and forming a plurality of ring trenches in the scribe-line area that individually at least partially surround the individual die areas; forming digitlines in the digitline trenches; forming a conductive-wall construction in individual of the ring trenches and that at least partially surrounds one of the individual die areas, the conductive-wall construction extending through a majority of thickness of the semiconductor wafer and being directly electrically coupled with semiconductive material of the semiconductor wafer; and forming a memory-array region comprising memory cells in the individual die areas, individual of the memory cells being electrically coupled with individual of the digitlines.
19. 22 - 26 . (canceled)
20. 27 .: A method used in forming memory circuitry, comprising: fabricating a semiconductor wafer to have die areas and scribe-line area around individual of the die areas; in a single masking step, simultaneously forming capacitor trenches in the individual die areas and a plurality of ring trenches in the scribe-line area that individually at least partially surround the individual die areas; forming capacitors in the capacitor trenches; forming a conductive-wall construction in individual of the ring trenches and that at least partially surrounds one of the individual die areas, the conductive-wall construction extending through a majority of thickness of the semiconductor wafer and being directly electrically coupled with semiconductive material of the semiconductor wafer; and forming a memory-array region comprising memory cells in the individual die areas, individual of the memory cells comprising one of the capacitors.

Description

TECHNICAL FIELD Embodiments disclosed herein pertain to memory circuitry and to methods used in forming memory circuitry. BACKGROUND Memory is one type of integrated circuitry and is used in computer systems for storing data. Memory may be fabricated in one or more arrays of individual memory cells. Memory cells may be written to, or read from, using digitlines (which may also be referred to as bitlines, data lines, or sense lines) and access lines (which may also be referred to as wordlines). The sense lines may conductively interconnect memory cells along columns of the array, and the access lines may conductively interconnect memory cells along rows of the array. Each memory cell may be uniquely addressed through the combination of a sense line and an access line. Memory cells may be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for extended periods of time in the absence of power. Non-volatile memory is conventionally specified to be memory having a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed/rewritten to maintain data storage. Volatile memory may have a retention time of milliseconds or less. Regardless, memory cells are configured to retain or store memory in at least two different selectable states. In a binary system, the states are considered as either a “0” or a “1”. In other systems, at least some individual memory cells may be configured to store more than two levels or states of information. Memory cells may be arranged or arrayed in several manners including essentially horizontally in a single plane or alternately, for example, in a vertical stack (e.g., along a z direction) comprising a three-dimensional (3D) memory-array region having horizontal tiers in which individual memory cells are received (e.g., arrayed in x and y directions). The stack in the 3D memory-array region comprises vertically-alternating insulative tiers and conductive tiers (e.g., as part of memory-cell tiers) that extend into a stair-step region. The stair-step region includes individual “stairs” (alternately termed “steps” or “stair-steps”) that define contact regions of conductive lines of individual of the conductive tiers to which vertical conductive vias can contact to provide electrical access to/from those conductive lines. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagrammatic schematic of a DRAM memory array and peripheral circuitry in accordance with the prior art and in accordance with an embodiment of the invention. FIG. 2 is an enlargement of a portion of FIG. 1. FIGS. 3-41 are diagrammatic sequential sectional and/or enlarged views of a construction, or portions thereof or alternate and/or additional embodiments, in process in accordance with some embodiments of the invention. DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS Embodiments of the invention encompass memory circuitry (e.g., DRAM) regardless of orientation (e.g., either horizontal or vertical). In some ideal embodiments, the memory circuitry comprises vertically-alternating insulative tiers and memory-cell tiers, with memory cells in the memory-cell tiers individually comprising a capacitor and a horizontally-oriented transistor. Embodiments of the invention also encompass methods used in forming memory circuitry. Example embodiments are described with reference to FIGS. 1-41. One example prior art schematic diagram of DRAM circuitry, and in accordance with an embodiment of the invention, is shown in FIGS. 1 and 2. FIG. 2 shows example memory cells MC individually comprising a transistor T and a capacitor C. One electrode of capacitor C is directly electrically coupled to a suitable potential (e.g., ground) and the other capacitor electrode is contacted with or comprises one of the source/drain regions of transistor T. The other source/drain region of transistor T is directly electrically coupled with a digitline/sense line 130 or 131 (also individually designated as DL). The gate of transistor T is directly electrically coupled with (e.g., comprises part thereof) a wordline/access line WL. FIG. 1 shows digitlines 130 and 131 extending from one of opposite sides 100 and 200 of a memory array area 10 into a peripheral circuitry area 113 that is aside memory array area 10. Digitlines 130 and 131 individually directly electrically couple with a sense amp SA on opposite sides 100 and 200 of array area 10 within peripheral circuitry area 113. Sense amps SA could be on only one side or all directly above or directly below memory array area 10. Non-schematic structure embodiments as shown herein in FIG. 3+ have the wordlines/access lines running horizontally and the digitlines/sense lines running vertically. Referring to FIGS. 3-5, an example semiconductor wafer 6 comprises a base substrate 11 and which may comprise any one or more of conductive/conductor/conducting, semiconductive/semiconductor/semiconducting, and insulative/insulator/insulating (i.e., electrical