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US-20260130230-A1 - SEMICONDUCTOR PACKAGE

US20260130230A1US 20260130230 A1US20260130230 A1US 20260130230A1US-20260130230-A1

Abstract

A semiconductor package may include: a first double-chip structure including a first semiconductor chip, a second semiconductor chip, a first scribe lane region dividing the first semiconductor chip and the second semiconductor chip, and a first through hole in the first scribe lane region; a second double-chip structure on the first double-chip structure, the second double-chip structure including a third semiconductor chip, a fourth semiconductor chip, a second scribe lane region dividing the third semiconductor chip and the fourth semiconductor chip, and a second through hole in the second scribe lane region; first conductive connection members between the first and second double-chip structures and configured to electrically connect the first and third semiconductor chips and the second and fourth semiconductor chips; and a molding member on the first double-chip structure and the second double-chip structure and in the first through hole and the second through hole.

Inventors

  • Hyeseon PARK
  • Yongkwan LEE

Assignees

  • SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date
20260507
Application Date
20251024
Priority Date
20241101

Claims (20)

  1. 1 . A semiconductor package, comprising: a first double-chip structure comprising a first semiconductor chip, a second semiconductor chip, and a first scribe lane region dividing the first semiconductor chip and the second semiconductor chip, wherein the first double-chip structure further includes at least one first through hole in the first scribe lane region; a second double-chip structure on the first double-chip structure, the second double-chip structure comprising a third semiconductor chip on the first semiconductor chip, a fourth semiconductor chip on the second semiconductor chip, and a second scribe lane region dividing the third semiconductor chip and the fourth semiconductor chip, wherein the second double-chip structure further includes at least one second through hole in the second scribe lane region; a plurality of first conductive connection members between the first double-chip structure and the second double-chip structure, the plurality of first conductive connection members configured to electrically connect the first semiconductor chip and the third semiconductor chip and configured to electrically connect the second semiconductor chip and the fourth semiconductor chip; and a molding member on the first double-chip structure and the second double-chip structure and in the at least one first through hole and the at least one second through hole.
  2. 2 . The semiconductor package of claim 1 , wherein, in a plan view of the semiconductor package, the at least one first through hole and the at least one second through hole overlap with each other.
  3. 3 . The semiconductor package of claim 1 , wherein, in a plan view of the semiconductor package, the at least one first through hole and the at least one second through hole are alternatively arranged with respect to each other.
  4. 4 . The semiconductor package of claim 1 , wherein each of the at least one first through hole comprises a first diameter, and each of the at least one second through hole comprises a second diameter that is equal to the first diameter.
  5. 5 . The semiconductor package of claim 1 , wherein each of the at least one first through hole comprises a first diameter, and each of the at least one second through hole comprises a second diameter that is different from the first diameter.
  6. 6 . The semiconductor package of claim 1 , further comprising: a substrate structure comprising a mounting region, wherein the first double-chip structure and the second double-chip structure are on the mounting region, the first double-chip structure being between the mounting region and the second double-chip structure.
  7. 7 . The semiconductor package of claim 6 , wherein a first diameter of each of the at least one first through hole becomes narrower towards the substrate structure, and a second diameter of each of the at least one second through hole becomes narrower towards the substrate structure.
  8. 8 . The semiconductor package of claim 6 , wherein the first double-chip structure further comprises: a first through via in the first semiconductor chip, wherein the first through via is configured to electrically connect the substrate structure and the third semiconductor chip; and a second through via in the second semiconductor chip, wherein the second through via is configured to electrically connect the substrate structure and the fourth semiconductor chip.
  9. 9 . The semiconductor package of claim 6 , further comprising: a second conductive connection member between the substrate structure and the first double-chip structure, wherein the second conductive connection member is configured to electrically connect the substrate structure and the first double-chip structure.
  10. 10 . The semiconductor package of claim 9 , wherein the molding member is in a first gap between the substrate structure and the first double-chip structure, and in a second gap between the first double-chip structure and the second double-chip structure.
  11. 11 . A semiconductor package, comprising: a substrate structure comprising a mounting region; a first double-chip structure on the mounting region of the substrate structure, the first double-chip structure comprising: a pair of first semiconductor chips arranged along a first horizontal direction; a first scribe lane region dividing the pair of first semiconductor chips; and a first penetration portion penetrating the first scribe lane region; a second double-chip structure on the first double-chip structure, the second double-chip structure comprising: a pair of second semiconductor chips arranged along the first horizontal direction; a second scribe lane region dividing the pair of second semiconductor chips; and a second penetration portion penetrating the second scribe lane region; at least one first conductive connection member between the substrate structure and the first double-chip structure, wherein the at least one first conductive connection member is configured to electrically connect the substrate structure and the first double-chip structure; at least one second conductive connection member between the first double-chip structure and the second double-chip structure, wherein the at least one second conductive connection member is configured to electrically connect the first double-chip structure and the second double-chip structure; and a molding member on the substrate structure, the first double-chip structure, and the second double-chip structure, wherein the molding member is in the first penetration portion and the second penetration portion.
  12. 12 . The semiconductor package of claim 11 , wherein the first double-chip structure is connected to the substrate structure by the at least one first conductive connection member, and a first gap is between the substrate structure and the first double-chip structure, and wherein a portion of the molding member is within the first gap, the portion on the at least one first conductive connection member.
  13. 13 . The semiconductor package of claim 11 , wherein the second double-chip structure is connected to the first double-chip structure by the at least one second conductive connection member, and a second gap is between the first double-chip structure and the second double-chip structure, and wherein a portion of the molding member is within the second gap, the portion on the at least one second conductive connection member.
  14. 14 . The semiconductor package of claim 11 , wherein the pair of first semiconductor chips comprises a first-first semiconductor chip and a first-second semiconductor chip, and wherein the pair of second semiconductor chips comprises: a second-first semiconductor chip on the first-first semiconductor chip; and a second-second semiconductor chip on the first-second semiconductor chip.
  15. 15 . The semiconductor package of claim 14 , wherein the first double-chip structure further comprises: at least one first through via in the first-first semiconductor chip, the at least one first through via configured to electrically connect the substrate structure and the second-first semiconductor chip; and at least one second through via in the first-second semiconductor chip, the at least one second through via configured to electrically connect the substrate structure and the second-second semiconductor chip.
  16. 16 . The semiconductor package of claim 11 , wherein the first penetration portion includes a plurality of first through holes arranged along a second horizontal direction perpendicular to the first horizontal direction, and wherein the second penetration portion includes a plurality of second through holes arranged along the second horizontal direction.
  17. 17 . The semiconductor package of claim 16 , wherein, in a plan view of the semiconductor package, the plurality of first through holes and the plurality of second through holes overlap with each other.
  18. 18 . The semiconductor package of claim 16 , wherein, in a plan view of the semiconductor package, the plurality of first through holes and the plurality of second through holes are alternatively arranged with respect to each other.
  19. 19 . The semiconductor package of claim 11 , wherein at least one from among the first penetration portion and the second penetration portion includes a through slit, wherein, in a plan view of the semiconductor package, the through slit comprises a polygonal shape, and wherein the through slit extends in a second horizontal direction perpendicular to the first horizontal direction.
  20. 20 . A semiconductor package, comprising: a substrate structure comprising a mounting region; a first double-chip structure on the mounting region of the substrate structure, the first double-chip structure comprising a first semiconductor chip, a second semiconductor chip, and a first scribe lane region dividing the first semiconductor chip and the second semiconductor chip; a second double-chip structure on the first double-chip structure, the second double-chip structure comprising a third semiconductor chip on the first semiconductor chip, a fourth semiconductor chip on the second semiconductor chip, and a second scribe lane region dividing the third semiconductor chip and the fourth semiconductor chip; at least one first conductive connection member between the substrate structure and the first double-chip structure, wherein a first gap is between the substrate structure and the first double-chip structure, and the at least one first conductive connection member is configured to electrically connect the substrate structure and the first double-chip structure; at least one second conductive connection member between the first double-chip structure and the second double-chip structure, wherein a second gap is between the first double-chip structure and the second double-chip structure, and the at least one second conductive connection member is configured to electrically connect the first double-chip structure and the second double-chip structure; and a molding member on the substrate structure, the first double-chip structure, and the second double-chip structure, wherein the first double-chip structure further includes at least one first through hole in the first scribe lane region, wherein the second double-chip structure further includes at least one second through hole in the second scribe lane region, and wherein the molding member is in the first gap, the second gap, the at least one first through hole, and the at least one second through hole.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2024-0153445, filed on Nov. 1, 2024, in the Korean Intellectual Property Office (KIPO), the contents of which are herein incorporated by reference in their entirety. BACKGROUND 1. Field Some example embodiments of the present disclosure relate to a semiconductor package. More particularly, some example embodiments of the present disclosure relate to a semiconductor package including a double-chip structure with a pair of semiconductor chips and a molding member covering the double-chip structure. 2. Description of Related Art In a molded underfill (MUF) process, the higher a chip is located among stacked chips, the faster a molding material can be filled. Additionally, in the MUF process, a peripheral region of the chip may be quickly filled with the molding material compared to a central region of the same chip. Accordingly, the central region of the lowest chip among the stacked chips may be filled with the molding material late compared to the peripheral region of the uppermost chip, so voids may occur in a portion of the molding material below the lowest chip among the stacked chips. In addition, since the peripheral region portion of the uppermost chip is filled with the molding material first, warpage may occur during the molding process, and as a result, bumps of the lowest chip may be pressed. SUMMARY According to some example embodiments of the present disclosure, a semiconductor package may be provided and have a passage through which a molding material moves to prevent a void from occurring in the molding material. According to some embodiments of the present disclosure, a semiconductor package may include: a first double-chip structure including a first semiconductor chip, a second semiconductor chip, and a first scribe lane region dividing the first semiconductor chip and the second semiconductor chip, and at least one first through hole in the first scribe lane region; a second double-chip structure on the first double-chip structure, the second double-chip structure including a third semiconductor chip on the first semiconductor chip, a fourth semiconductor chip on the second semiconductor chip, and a second scribe lane region dividing the third semiconductor chip and the fourth semiconductor chip, and at least one second through hole in the second scribe lane region; a plurality of first conductive connection members between the first double-chip structure and the second double-chip structure, the plurality of first conductive connection members configured to electrically connect the first semiconductor chip and the third semiconductor chip and configured to electrically connect the second semiconductor chip and the fourth semiconductor chip; and a molding member on the first double-chip structure and the second double-chip structure and in the at least one first through hole and the at least one second through hole. According to some embodiments of the present disclosure, a semiconductor package may include: a substrate structure including a mounting region; a first double-chip structure on the mounting region of the substrate structure, the first double-chip structure including: a pair of first semiconductor chips arranged along a first horizontal direction; a first scribe lane region dividing the pair of first semiconductor chips; and a first penetration portion penetrating the first scribe lane region; a second double-chip structure on the first double-chip structure, the second double-chip structure including: a pair of second semiconductor chips arranged along the first horizontal direction; a second scribe lane region dividing the pair of second semiconductor chips; and a second penetration portion penetrating the second scribe lane region; at least one first conductive connection member between the substrate structure and the first double-chip structure, wherein the at least one first conductive connection member is configured to electrically connect the substrate structure and the first double-chip structure; at least one second conductive connection member between the first double-chip structure and the second double-chip structure, wherein the at least one second conductive connection member is configured to electrically connect the first double-chip structure and the second double-chip structure; and a molding member on the substrate structure, the first double-chip structure, and the second double-chip structure, wherein the molding member is in the first penetration portion and the second penetration portion. According to some embodiments of the present disclosure, a semiconductor package may include: a substrate structure including a mounting region; a first double-chip structure on the mounting region of the substrate structure, the first double-chip structure including a first semiconductor chip, a second semiconductor chip, and a first scribe lan