US-20260130232-A1 - PACKAGING DEVICE INCLUDING BUMPS AND METHOD OF MANUFACTURING THE SAME

US20260130232A1US 20260130232 A1US20260130232 A1US 20260130232A1US-20260130232-A1

Abstract

A packaging device including bumps and a method of manufacturing the packaging device are presented. In the method of manufacturing a packaging device, a dielectric layer that covers a packaging base is formed and a lower layer is formed over a packaging base including first and second connecting pads. A plurality of dummy bumps that overlaps with the dielectric layer is formed. A sealing pattern that covers the dummy bumps, filling areas between the dummy bumps, is formed. A lower layer pattern in which the plurality of dummy bumps have been disposed is formed by removing portions of the lower layer that are exposed and do not overlap with the sealing pattern.

Inventors

Jae Jun Lee
Jong Yeon Kim
Jong Hoon Kim
Ju Heon YANG
Mi Seon Lee

Assignees

SK Hynix Inc.

Dates

Publication Date: 20260507
Application Date: 20251230
Priority Date: 20220927

Claims (7)

1 . A packaging device comprising: first and second connecting pads that are disposed in a packaging base; a dielectric layer that covers the packaging base and exposes the first and second connecting pads; a first lower layer pattern that is formed on the dielectric layer; and a plurality of dummy bumps that are disposed on the first lower layer pattern.
2 . The packaging device of claim 1 , wherein the dummy bumps are interconnected through the first lower layer pattern.
3 . The packaging device of claim 1 , wherein: the first lower layer pattern is bonded to the dielectric layer, and the dummy bumps and the first lower layer pattern are electrically isolated from the first and second connecting pads by the dielectric layer.
4 . The packaging device of claim 1 , further comprising: second lower layer patterns that are bonded to the first and second connecting pads, respectively; and connecting bumps that are bonded to the second lower layer patterns, respectively.
5 . The packaging device of claim 4 , wherein the second lower layer patterns comprise protruding portions that protrude away from the connecting bumps.
6 . The packaging device of claim 4 , wherein the first lower layer pattern and the second lower layer patterns comprise an under bump metallurgy (UBM) layer.
7 . The packaging device of claim 4 , wherein the packaging base comprises a semiconductor substrate or a printed circuit board (PCB).

Description

CROSS-REFERENCE TO RELATED APPLICATION The present application is a divisional application of U.S. patent application Ser. No. 18/186,284, filed on Mar. 20, 2023, which claims priority under 35 U.S.C. § 119(a) to Korean application number 10-2022-0122852, filed in the Korean Intellectual Property Office on Sep. 27, 2022, the entire contents of which applications are incorporated herein by reference. BACKGROUND The present disclosure relates to a semiconductor technology and, particularly, to a packaging device including bumps and a method of manufacturing the same. A packaging device may include a device in which a semiconductor device or an integrated circuit device is packaged. As performance of a semiconductor device, the degree of integration of semiconductor devices, and the speed of a semiconductor device are increased and the size of a semiconductor device is reduced, the number of connecting terminals or input/output (I/O) terminals for an interconnection that is required for the semiconductor device is increased. Accordingly, conductive bumps are adopted as connecting elements for the semiconductor device. For example, conductive bumps are adopted as connecting elements for a high bandwidth memory product. As the number and density of bumps are increased, the size of the bump is reduced. As the size of the bump is reduced, a failure in which bumps are detached from a semiconductor device without maintaining the state in which the bumps have been coupled to the semiconductor device may occur. SUMMARY An embodiment may present a method of manufacturing a packaging device, including forming, on a packaging base including first and second connecting pads, a dielectric layer that covers the packaging base and exposes the first and second connecting pads, forming a lower layer that covers the dielectric layer and the first and second connecting pads, forming a plurality of dummy bumps that overlaps with the dielectric layer, forming a sealing pattern that fills areas between the dummy bumps, and forming a first lower layer pattern on which the plurality of dummy bumps have been disposed by removing portions of the lower layer that are exposed and do not overlap with the sealing pattern. An embodiment may present a packaging device, including first and second connecting pads that are disposed in a packaging base, a dielectric layer that covers the packaging base and exposes the first and second connecting pads, a first lower layer pattern that is formed on the dielectric layer, and a plurality of dummy bumps that are disposed on the first lower layer pattern. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional view illustrating that bumps in a method of manufacturing a packaging device according to an embodiment have been formed. FIGS. 2 to 4 are schematic cross-sectional views illustrating detailed process steps of forming the bumps in FIG. 1. FIG. 5 is a schematic cross-sectional view illustrating that a sealing pattern in a method of manufacturing a packaging device according to an embodiment has been formed. FIG. 6 is a schematic cross-sectional view illustrating that lower layer patterns in a method of manufacturing a packaging device according to an embodiment have been formed. FIG. 7 is a schematic cross-sectional view illustrating a packaging device according to an embodiment. FIG. 8 is a schematic cross-sectional view illustrating that a sealing pattern in a method of manufacturing a packaging device according to another embodiment has been formed. FIG. 9 is a schematic cross-sectional view illustrating that lower layer patterns in a method of manufacturing a packaging device according to another embodiment are formed. FIG. 10 is a schematic cross-sectional view illustrating a device package according to another embodiment. FIG. 11 is a block diagram illustrating an electronic system using a memory card including a packaging device according to an embodiment. FIG. 12 is a block diagram illustrating an electronic system including a packaging device according to an embodiment. DETAILED DESCRIPTION Terms that are used in the description of examples of this application are terms selected by taking into consideration functions in proposed embodiments, and the meanings of the terms may be different depending on a user, an operator's intention or practice in the technical field. The meaning of a term used follows the definition of the term if the term has been specifically defined in this specification and may be interpreted as a meaning which may be commonly recognized by those skilled in the art if the term has not been specifically defined. In the description of examples of this application, terms, such as a “first”, a ‘second”, a “side”, a “top”, and a “bottom or lower”, are used to distinguish between members and are not used to limit the members themselves or to mean a specific order. A semiconductor substrate may denote a semiconductor wafer on which electronic parts and eleme