US-20260130233-A1 - INTERPOSER STRUCTURE AND MANUFACTURING METHOD THEREFOR

Abstract

A method for fabricating an interposer structure includes: providing a substrate; forming a first opening and filling a first conductive layer in the first opening; forming a first dielectric layer on a first surface of the substrate and forming a first redistribution metal layer in the first dielectric layer; forming a second opening and filling a second conductive layer in the second opening; forming a second dielectric layer on a second surface of the substrate and forming a second redistribution metal layer in the second dielectric layer. Through the redistribution metal layer for wiring is formed on both sides of the substrate in the thickness direction, the high-intensity interconnection requirements can be satisfied. The first opening and the second opening are formed from both sides of the substrate in the thickness direction, respectively, and communicate with each other to make up a TSV hole.

Inventors

• Guoliang YE
• Sheng Hu
• Qiong Zhan
• Jun Zhou
• Peng Sun
• Daohong YANG

Assignees

• WUHAN XINXIN SEMICONDUCTOR MANUFACTURING CO., LTD.

Dates

Publication Date

20260507

Application Date

20221208

Priority Date

20221025

Claims (19)

1. 1 . A method for fabricating an interposer structure, comprising: providing a substrate having a first surface and a second surface that is opposite to the first surface, forming a first opening in the first surface, wherein the first opening extends from the first surface into the substrate, filling a first conductive layer in the first opening; forming a first dielectric layer on the first surface of the substrate; and forming a first redistribution metal layer in the first dielectric layer, wherein the first redistribution metal layer is electrically connected to the first conductive layer; bonding a side of the first dielectric layer that is away from the substrate to a first carrier; forming a second opening in the second surface of the substrate, wherein the second opening extends from the second surface into the substrate so as to communicate with the first opening; and filling a second conductive layer in the second opening, wherein the second conductive layer is electrically connected to the first conductive layer; forming a second dielectric layer on the second surface of the substrate; and forming a second redistribution metal layer in the second dielectric layer, wherein the second redistribution metal layer is electrically connected to the second conductive layer; forming a first bonding structure on a side of the second dielectric layer that is away from the substrate, wherein the first bonding structure is electrically connected to the second redistribution metal layer; and bonding the first bonding structure to a second carrier, removing the first carrier and then forming a second bonding structure on a side of the first dielectric layer that is away from the substrate, and removing the second carrier, wherein the second bonding structure is electrically connected to the first redistribution metal layer.
2. 2 . The method for fabricating the interposer structure of claim 1 , wherein in a cross-section taken perpendicular to the first surface, the first opening has a minimum cross-sectional width≥10 μm and a depth≥100 μm.
3. 3 . The method for fabricating an interposer structure of claim 1 , wherein before forming the second opening in the second surface of the substrate, the substrate is thinned from a side of the second surface, and wherein the thinned substrate has a thickness≥150 μm.
4. 4 . The method for fabricating an interposer structure of claim 1 , wherein in a cross-section taken perpendicular to the first surface, the second opening has a minimum cross-sectional width≥5 μm and a depth≥50 μm.
5. 5 . The method for fabricating an interposer structure of claim 1 , wherein the first bonding structure and/or the second bonding structure is/are a metal bump.
6. 6 . The method for fabricating an interposer structure of claim 1 , wherein a pitch of the second bonding structure is smaller than a pitch of the first bonding structure, wherein the second bonding structure is configured to bond a chip, and the first bonding structure is configured to bond a printed circuit board.
7. 7 . The method for fabricating an interposer structure of claim 1 , wherein the substrate is a silicon substrate.
8. 8 . An interposer structure, comprising: a substrate having a first surface and a second surface that is opposite to the first surface; a first opening, wherein the first opening extends from the first surface into the substrate and is filled with a first conductive layer; a first dielectric layer located on the first surface of the substrate, wherein a first redistribution metal layer is formed in the first opening and is electrically connected to the first conductive layer; a second opening, wherein the second opening extends from the second surface into the substrate and communicates with the first opening, and wherein a second conductive layer is filled in the second opening and is electrically connected to the first conductive layer; a second dielectric layer located on the second surface of the substrate, wherein a second redistribution metal layer is formed in the second dielectric layer and is electrically connected to the second conductive layer; and a first bonding structure and a second bonding structure, wherein the first bonding structure is located on a side of the second dielectric layer away from the substrate and is electrically connected to the second redistribution metal layer, and wherein the second bonding structure is located on a side of the first dielectric layer away from the substrate and is electrically connected to the first redistribution metal layer.
9. 9 . The interposer structure of claim 8 , wherein a pitch of the second bonding structure is smaller than a pitch of the first bonding structure, and wherein the second bonding structure is configured to bond a chip, and the first bonding structure is configured to bond a printed circuit board.
10. 10 . The interposer structure of claim 8 , wherein the substrate has a thickness≥150 μm.
11. 11 . The method for fabricating an interposer structure of claim 1 , wherein the first bonding structure and/or the second bonding structure is/are a hybrid bonding structure.
12. 12 . The method for fabricating an interposer structure of claim 1 , wherein the first opening has a depth-to-width ratio≥10:1, and wherein the second opening has a depth-to-width ratio≥10:1.
13. 13 . The method for fabricating an interposer structure of claim 1 , wherein the first opening has a depth-to-width ratio≥10:1, and wherein the second opening has a depth-to-width ratio<10:1.
14. 14 . The method for fabricating an interposer structure of claim 1 , wherein the first opening has a depth-to-width ratio<10:1, and wherein the second opening has a depth-to-width
15. 15 . The method for fabricating an interposer structure of claim 1 , wherein the first opening has a depth-to-width ratio<10:1, and wherein the second opening has a depth-to-width ratio<10:1.
16. 16 . The interposer structure of claim 8 , wherein the first opening has a depth-to-width ratio≥10:1, and wherein the second opening has a depth-to-width ratio≥10:1.
17. 17 . The interposer structure of claim 8 , wherein the first opening has a depth-to-width ratio≥10:1, and wherein the second opening has a depth-to-width ratio<10:1.
18. 18 . The interposer structure of claim 8 , wherein the first opening has a depth-to-width ratio<10:1, and wherein the second opening has a depth-to-width ratio≥10:1.
19. 19 . The interposer structure of claim 8 , wherein the first opening has a depth-to-width ratio<10:1, and wherein the second opening has a depth-to-width ratio<10:1.

Description

TECHNICAL FIELD The present invention relates to the field of integrated circuit (IC) fabrication technology and, in particular, to an interposer structure and a method for fabricating the same. BACKGROUND Packaging technology came into being with the invention of integrated circuits (ICs) and is used mainly for power distribution, signal distribution, heat dissipation and protection. With the advancement of chip technology, packaging technology continues to innovate, the density of packaging and interconnections keeps increasing, the thickness of packages keeps decreasing, and three-dimensional packaging and system-in-package methods are constantly evolving. As ICs are used in more and more fields, more demanding requirements are imposed on advanced packaging by some emerging applications such as smart phones, Internet of things (IoT), automotive electronics, high-performance computing, 5G and artificial intelligence. The rapid development of packaging technology and continuous emergence of innovations have given birth to silicon interposers with through-silicon vias (TSVs) and densely arranged metal traces for addressing the problems of an insufficient wiring density associated with conventional interposers. In conventional silicon interposer, a redistribution metal layer (RDL) is only formed on one side of the substrate. The formation method involves forming a blind hole on the front side of the substrate and filling it with conductive material to form TSV (Through-Silicon Vias), followed by forming a redistribution metal layer on the front side to tap the TSVs. The TSVs do not extend through the substrate, and it is necessary to subsequently thin the substrate from the backside until the bottom of the TSV is exposed and connect it to an IC substrate by metal bump. Use in combination with the IC substrate can provide higher strength. However, the number of redistribution metal layers tends to fail to meet the requirements of a high-density interconnection design. Further, in the silicon interposer, limited to the TSV′ depth, the thinned substrate has to have a small thickness of silicon. Consequently, the substrate tends to deform or even crack at high temperatures due to high coefficient of thermal expansion (CTE) sensitivity of silicon. SUMMARY OF THE INVENTION It is an object of the present invention to provide an interposer structure and a method for fabricating the same, in which redistribution metal layer for wiring is formed on both sides of the substrate in the thickness direction, satisfying the high-intensity interconnection requirements. Moreover, the first opening and the second opening are formed from both sides of the substrate in the thickness direction, respectively, and communicate with each other to make up a TSV hole. Thus, the interposer is allowed to have a large thickness, overcoming the depth-to-width ratio limitations of galvanic metal filling and other techniques involved in TSV formation. Moreover, the interposer is made less prone to deformation even at high temperatures, and can even dispense with the use of a separate IC carrier, resulting in cost and power savings. The present invention provides a method for fabricating an interposer structure, comprising: providing a substrate having a first surface and a second surface that is opposite to the first surface, forming a first opening in the first surface, wherein the first opening extends from the first surface into the substrate, filling a first conductive layer in the first opening; forming a first dielectric layer on the first surface of the substrate; and forming a first redistribution metal layer in the first dielectric layer, wherein the first redistribution metal layer is electrically connected to the first conductive layer;bonding a side of the first dielectric layer that is away from the substrate to a first carrier; forming a second opening in the second surface of the substrate, wherein the second opening extends from the second surface into the substrate so as to communicate with the first opening; and filling a second conductive layer in the second opening, wherein the second conductive layer is electrically connected to the first conductive layer;forming a second dielectric layer on the second surface of the substrate; and forming a second redistribution metal layer in the second dielectric layer, wherein the second redistribution metal layer is electrically connected to the second conductive layer;forming a first bonding structure on a side of the second dielectric layer that is away from the substrate, wherein the first bonding structure is electrically connected to the second redistribution metal layer; andbonding the first bonding structure to a second carrier, removing the first carrier and then forming a second bonding structure on a side of the first dielectric layer that is away from the substrate, and removing the second carrier, wherein the second bonding structure is electrically connected to the firs