US-20260130235-A1 - Package with Epitaxial Layer of Electronic Component Spaced from a Front-side Connection Body by less than 50 μm

Abstract

A package includes an at least partially electrically conductive front-side connection body and an electronic component having an epitaxial layer and being assembled with the front-side connection body. A distance between the epitaxial layer and the front-side connection body is less than 50 μm. A method of manufacturing the package is also described.

Inventors

• Marcus Böhm
• Hans-Joachim Schulze
• Horst Theuss
• Saurabh Roy
• Markus Gröner
• Max Falkowski
• Sergey ANANIEV
• Ralf Otremba
• Alexander Heinrich
• Evelyn Napetschnig

Assignees

• INFINEON TECHNOLOGIES AG

Dates

Publication Date

20260507

Application Date

20251103

Priority Date

20241104

Claims (20)

1. 1 . A package, comprising: a front-side connection body that is at least partially electrically conductive; and an electronic component having an epitaxial layer and being assembled with the front-side connection body; wherein a distance between the epitaxial layer and the front-side connection body is less than 50 μm.
2. 2 . The package of claim 1 , wherein a surface of the front-side connection body facing the electronic component is curved in a convex fashion.
3. 3 . The package of claim 1 , further comprising: an electrically conductive connection medium connecting the electronic component with the front-side connection body, wherein the connection medium is made of a material having a Young modulus value of at least 60 GPa at 20° C.
4. 4 . The package of claim 3 , wherein at least one of: the connection medium comprises a diffusion bonding material; the connection medium comprises a sinter material; and the connection medium has a thickness of not more than 20 μm.
5. 5 . The package of claim 1 , wherein the front-side connection body is a clip.
6. 6 . The package of claim 5 , wherein a lateral surface of the clip is structured to enhance stress applied to the electronic component.
7. 7 . The package of claim 1 , wherein the front-side connection body is a carrier on which the electronic component is mounted.
8. 8 . The package of claim 7 , wherein a surface of the carrier facing a surface of the electronic component is curved in a concave fashion.
9. 9 . The package of claim 1 , further comprising: a carrier on which the electronic component is mounted.
10. 10 . The package of claim 9 , wherein a surface of the carrier facing a surface of the electronic component is curved in a concave fashion.
11. 11 . The package of claim 9 , further comprising: a further electrically conductive connection medium connecting the electronic component with the carrier, wherein a Young modulus value of the further electrically conductive connection medium is at least 60 GPa at 20° C.
12. 12 . The package of claim 1 , wherein the front-side connection body is an interposer.
13. 13 . The package of claim 1 , wherein the electronic component comprises a bulk layer and a metallization layer with the epitaxial layer in between, and wherein the epitaxial layer is located closer to the front-side connection body than the bulk layer.
14. 14 . The package of claim 13 , wherein thicknesses of the epitaxial layer, the metallization layer, a connection medium between the electronic component and the front-side connection body, and the front-side connection body have a relational link of 1 to at least 2.
15. 15 . The package of claim 14 , wherein at least one of: the thickness of the epitaxial layer is in a range from 5 μm to 70 μm; the thickness of the metallization layer is in a range from 1 μm to 20 μm; the thickness of the connection medium is in a range from 0.5 μm to 50 μm; and the thickness of the front-side connection body is in a range from 100 μm to 3000 μm.
16. 16 . The package of claim 1 , wherein the distance between the epitaxial layer and the front-side connection body is less than 20 μm.
17. 17 . The package of claim 1 , wherein the electronic component is at least one of a semiconductor chip, a transistor chip, a power chip, a vertical chip, a silicon carbide chip, a chip with super-junction, a unipolar chip, a bipolar chip, and a chip in flip-chip configuration.
18. 18 . The package of claim 1 , wherein the front-side connection body and the electronic component are designed so that stress applied to the electronic component is at least 200 MPa.
19. 19 . The package of claim 1 , wherein the front-side connection body, the electronic component and an additional carrier on which a back-side of the electronic component is mounted are designed for applying stress to the electronic component at both opposing main surfaces thereof.
20. 20 . A method of manufacturing a package, the method comprising: assembling an at least partially electrically conductive front-side connection body with an electronic component having an epitaxial layer; and arranging the front-side connection body with respect to the electronic component so that a distance between the epitaxial layer and the front-side connection body is less than 50 μm.

Description

TECHNICAL FIELD Various embodiments relate generally to a package and a method of manufacturing a package. BACKGROUND Packages may be denoted as electronic components with electrical connections extending out of the package and being mountable on an electronic periphery, for instance on a printed circuit board. Packaging cost is an important driver for the industry. Related with this are performance, dimensions and reliability. The different packaging solutions are manifold and have to address the needs of the application. In a transistor-type electronic component of a package, Rdson is a quality parameter which stands for drain-source on resistance. For example, Rdson may be an indication for the total resistance between the drain and the source in a field-effect transistor, such as a metal oxide semiconductor field-effect transistor (MOSFET) or a junction field-effect transistor (JFET, i.e. a field-effect transistor which may be exclusively voltage-controlled and which may be used for example as electrically controlled switch or resistor), when being in an ‘on’ state. In particular, Rdson may be used as a basis for a maximum current rating of the electronic component and is also associated with current loss. To put it shortly, the lower the Rdson, the better. However, Rdson of conventional packages may be high. SUMMARY There may be a need for a package with high electrical performance. In particular, there may be a need for a package with low drain-source on resistance. According to an exemplary embodiment, a package is provided which comprises an at least partially electrically conductive front-side connection body, and an electronic component having an epitaxial layer and being assembled with the front-side connection body, wherein a distance between the epitaxial layer and the front-side connection body is less than 50 μm. According to another exemplary embodiment, a method of manufacturing a package is provided, wherein the method comprises assembling an at least partially electrically conductive front-side connection body with an electronic component having an epitaxial layer, and arranging the front-side connection body with respect to the electronic component so that a distance between the epitaxial layer and the front-side connection body is less than 50 μm. According to an exemplary embodiment, a package (which may be a semiconductor power package) may be equipped with a partially or entirely electrically conductive front-side connection body (such as a clip, a leadframe structure or another more generic substrate) establishing a connection with a front-side (at which an active region may be formed) of an electronic component. Said electronic component may comprise an epitaxial layer or active region facing the front-side connection body. A connection between the front-side connection body and the electronic component may be established, for instance, by soldering or sintering. Advantageously, a distance between the epitaxial layer and the front-side connection body may be less than 50 μm. It has been found that such a small distance between active region and connection body at the front-side of the electronic component (for example using common interconnect technologies such as soldering, sintering or (more specifically) diffusion soldering) may create a considerable amount of mechanical strain at the front-side of the electronic component which may lead to a significant decrease of the drain-source on resistance. Thus, a package may be obtained which has a low Rdson value and consequently an excellent maximum current rating as well as low current loss. Also in embodiments in which the electronic component does not comprise a transistor, strain added to the front-side of the electronic component may also have a positive impact on the electrical performance of the package. In particular, a semiconductor material may be included in the electronic component which has the function of modulating the current flow. In particular a structure with such a semiconductor content may benefit from the proposed strain engineering concept. In the following, further exemplary embodiments of the package and the method will be explained. In the context of the present application, the term “package” may particularly denote an electronic device which may comprise one or more electronic components mounted on a carrier or with another front-side and/or back-side connection body. Said constituents of the package may be optionally encapsulated at least partially by an encapsulant. Further optionally, one or more electrically conductive interconnect bodies (such as bond wires) may be implemented in a package, for instance for electrically coupling the electronic component with the carrier and/or with leads. In the context of the present application, the term “electronic component” may in particular encompass a semiconductor chip (in particular a power semiconductor chip), an active electronic device (such as a transistor