US-20260130236-A1 - CHIP ON FILM PACKAGE AND ELECTRONIC DEVICE INCLUDING THE SAME

US20260130236A1US 20260130236 A1US20260130236 A1US 20260130236A1US-20260130236-A1

Abstract

A chip on film package may include: a substrate; a semiconductor chip on the substrate; first wires extending, on the substrate, to an edge of a first side of the substrate from a portion of the first wires overlapping with an edge of a first side of the semiconductor chip; second wires extending, on the substrate, to an edge of a second side of the substrate from a portion of the second wires overlapping with an edge of a second side of the semiconductor chip; first bumps connecting the first wires and the semiconductor chip; first dummy patterns spaced apart from at least some of the first bumps, the first dummy patterns being nearer than the first bumps to a center portion of the semiconductor chip, wherein the first dummy patterns are respectively spaced apart from first internal bumps, among the first bumps, in a second direction.

Inventors

NARAE SHIN
Jeong-kyu Ha

Assignees

SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date: 20260507
Application Date: 20250407
Priority Date: 20241105

Claims (20)

1 . A chip on film package comprising: a substrate; a semiconductor chip on the substrate; first wires extending, on the substrate, to an edge of a first side of the substrate from a portion of the first wires overlapping with an edge of a first side of the semiconductor chip; second wires extending, on the substrate, to an edge of a second side of the substrate from a portion of the second wires overlapping with an edge of a second side of the semiconductor chip; first bumps connecting the first wires and the semiconductor chip; first dummy patterns spaced apart from at least some of the first bumps, the first dummy patterns being nearer than the first bumps to a center portion of the semiconductor chip, wherein the first bumps comprise: first external bumps spaced apart from each other in a first direction that is parallel to the edge of the first side of the semiconductor chip; and first internal bumps spaced apart from each other in the first direction, the first internal bumps being nearer than the first external bumps to the center portion of the semiconductor chip, and wherein the first dummy patterns are respectively spaced apart from the first internal bumps in a second direction that is perpendicular to the first direction.
2 . The chip on film package of claim 1 , wherein the first dummy patterns do not overlap with the first external bumps in the second direction.
3 . The chip on film package of claim 1 , wherein the first dummy patterns extend in the second direction and are spaced apart in the second direction from a center line passing through the center portion of the semiconductor chip, and wherein the first dummy patterns are between the center line and the first bumps.
4 . The chip on film package of claim 1 , further comprising: second bumps connecting the second wires and the semiconductor chip; and second dummy patterns spaced apart from the second bumps in the second direction, the second dummy patterns being nearer than the second bumps to the center portion of the semiconductor chip.
5 . The chip on film package of claim 4 , wherein the second dummy patterns do not overlap with the first dummy patterns in the second direction.
6 . The chip on film package of claim 4 , further comprising: a third wire connecting two of the first wires, two of the second wires, or one of the first wires and one of the second wires, wherein the first dummy patterns or the second dummy patterns are not disposed in a region overlapping with, in the second direction, a location in which any of the two of the first wires, two of the second wires, or the one of the first wires and the one of the second wires is connected to the third wire.
7 . The chip on film package of claim 1 , wherein each of the first dummy patterns extend in the second direction, and wherein lengths of the first dummy patterns in the second direction are greater than widths of the first dummy patterns in the first direction.
8 . The chip on film package of claim 7 , wherein the lengths of the first dummy patterns in the second direction are larger than a gap between one of the first wires and one of the first dummy patterns nearest to the one of the first wires, among the first dummy patterns.
9 . The chip on film package of claim 1 , wherein a gap between one of the first wires and one of the first dummy patterns nearest to the one of the first wires, among the first dummy patterns, is equal to or greater than 10 μm and equal to or less than 100 μm.
10 . The chip on film package of claim 1 , wherein widths of the first dummy patterns in the first direction are equal to or greater than 7 μm and equal to or less than 20 μm.
11 . The chip on film package of claim 1 , wherein a width of one of the first dummy patterns in the first direction is less than widths of each of the first bumps in the first direction.
12 . The chip on film package of claim 1 , wherein widths of each of the first dummy patterns in the first direction are equal to a width of one of the first wires in the first direction.
13 . The chip on film package of claim 1 , wherein the first dummy patterns and the first wires comprise a same material as each other.
14 . The chip on film package of claim 1 , wherein the first wires are spaced apart from each other in the first direction, and the chip on film package further comprises a third dummy pattern at an outer side of an outermost first wire among the first wires.
15 . The chip on film package of claim 14 , wherein the third dummy pattern extends in the second direction, and wherein a length of the third dummy pattern in the second direction is equal to or greater than a length, in the second direction, of an entire portion of one of the first wires that overlaps with the semiconductor chip in a third direction, perpendicular to the first direction and the second direction.
16 . An electronic device comprising: a printed circuit board; and a chip on film package comprising: an output pin on a first side of the chip on film package; and an input pin on a second side of the chip on film package, the input pin connecting the chip on film package and the printed circuit board; a substrate; a semiconductor chip on the substrate; first wires extending, on the substrate, to an edge of a first side of the substrate from a portion of the first wires overlapping with an edge of a first side of the semiconductor chip, wherein at least one of the first wires is connected to the output pin; second wires extending, on the substrate, to an edge of a second side of the substrate from a portion of the second wires overlapping with an edge of a second side of the semiconductor chip, wherein at least one of the second wires is connected to the input pin; first bumps connecting the first wires and the semiconductor chip; and first dummy patterns spaced apart from at least some of the first bumps, the first dummy patterns being nearer than the first bumps to a center portion of the semiconductor chip, wherein the first bumps comprise: first external bumps spaced apart from each other in a first direction that is parallel to the edge of the first side of the semiconductor chip; and first internal bumps spaced apart from each other in the first direction, the first internal bumps being nearer than the first external bumps to the center portion of the semiconductor chip, and wherein the first dummy patterns are respectively spaced apart from the first internal bumps in a second direction that is perpendicular to the first direction.
17 . The electronic device of claim 16 , wherein the first dummy patterns do not overlap with the first external bumps in the second direction.
18 . The electronic device of claim 16 , further comprising second bumps connecting the second wires and the semiconductor chip; and second dummy patterns spaced apart from the second bumps in the second direction, the second dummy patterns being nearer than the second bumps to the center portion of the semiconductor chip.
19 . The electronic device of claim 18 , further comprising a third wire connecting two of the first wires, two of the second wires, or one of the first wires and one of the second wires, wherein the first dummy patterns and the second dummy patterns are not disposed in a region overlapping with, in the second direction, a location in which any of the two of the first wires, two of the second wires, or the one of the first wires and the one of the second wires is connected to the third wire.
20 . A chip on film package comprising: a substrate; a semiconductor chip on the substrate; first wires extending, on the substrate, to an edge of a first side of the substrate from a portion first of the first wires overlapping with an edge of a first side of the semiconductor chip; second wires extending, on the substrate, to an edge of a second side of the substrate from a portion of the second wires overlapping with an edge of a second side of the semiconductor chip; a first protection layer on at least a region of the first wires and the second wires; a second protection layer in a gap between the substrate and the semiconductor chip; first bumps connecting the first wires and the semiconductor chip; second bumps connecting the second wires and the semiconductor chip; and first dummy patterns spaced apart from at least some of the first bumps, the first dummy patterns being nearer than the first bumps to a center portion of the semiconductor chip, wherein the first bumps comprise: first external bumps spaced apart from each other in a first direction that is parallel to the edge of the first side of the semiconductor chip; and first internal bumps spaced apart from each other in the first direction, the first internal bumps being nearer than the first external bumps to the center portion of the semiconductor chip, and wherein each of the first dummy patterns comprise a quadrangular shape extending in a second direction that is perpendicular to the first direction, and the first dummy patterns are respectively spaced apart from the first internal bumps in the second direction.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0155572, filed in the Korean Intellectual Property Office on Nov. 5, 2024, the disclosure of which is incorporated herein by reference in its entirety. BACKGROUND 1. Field Some embodiments of the present disclosure relate to a chip on film package. 2. Description of Related Art To cope with the recent trend of miniaturization, thinning, and lightening of electronic products, as a high-density semiconductor chip mounting technology, a chip on film (COF) package technology using a flexible film substrate has been proposed. The COF package technology is attracting attention as a high-integration package technology because a semiconductor chip can be directly bonded to the film substrate by a flip-chip bonding method, can be connected to an external circuit through short leads, and can form a dense wiring pattern. SUMMARY According to some embodiments of the present disclosure, a chip on film package for increasing reliability may be provided. According to some embodiments of the present disclosure, a chip on film package may be provided and include: a substrate; a semiconductor chip on the substrate; first wires extending, on the substrate, to an edge of a first side of the substrate from a portion of the first wires overlapping with an edge of a first side of the semiconductor chip; second wires extending, on the substrate, to an edge of a second side of the substrate from a portion of the second wires overlapping with an edge of a second side of the semiconductor chip; first bumps connecting the first wires and the semiconductor chip; first dummy patterns spaced apart from at least some of the first bumps, the first dummy patterns being nearer than the first bumps to a center portion of the semiconductor chip, wherein the first bumps include: first external bumps spaced apart from each other in a first direction that is parallel to the edge of the first side of the semiconductor chip; and first internal bumps spaced apart from each other in the first direction, the first internal bumps being nearer than the first external bumps to the center portion of the semiconductor chip, and wherein the first dummy patterns are respectively spaced apart from the first internal bumps in a second direction that is perpendicular to the first direction. According to some embodiments of the present disclosure, an electronic device may be provided and include: a printed circuit board; and a chip on film package including: an output pin on a first side of the chip on film package; and an input pin on a second side of the chip on film package, the input pin connecting the chip on film package and the printed circuit board; a substrate; a semiconductor chip on the substrate; first wires extending, on the substrate, to an edge of a first side of the substrate from a portion of the first wires overlapping with an edge of a first side of the semiconductor chip, wherein at least one of the first wires is connected to the output pin; second wires extending, on the substrate, to an edge of a second side of the substrate from a portion of the second wires overlapping with an edge of a second side of the semiconductor chip, wherein at least one of the second wires is connected to the input pin; first bumps connecting the first wires and the semiconductor chip; and first dummy patterns spaced apart from at least some of the first bumps, the first dummy patterns being nearer than the first bumps to a center portion of the semiconductor chip, wherein the first bumps include: first external bumps spaced apart from each other in a first direction that is parallel to the edge of the first side of the semiconductor chip; and first internal bumps spaced apart from each other in the first direction, the first internal bumps being nearer than the first external bumps to the center portion of the semiconductor chip, and wherein the first dummy patterns are respectively spaced apart from the first internal bumps in a second direction that is perpendicular to the first direction. According to some embodiments of the present disclosure, a chip on film package may be provided and include: a substrate; a semiconductor chip on the substrate; first wires extending, on the substrate, to an edge of a first side of the substrate from a portion first of the first wires overlapping with an edge of a first side of the semiconductor chip; second wires extending, on the substrate, to an edge of a second side of the substrate from a portion of the second wires overlapping with an edge of a second side of the semiconductor chip; a first protection layer on at least a region of the first wires and the second wires; a second protection layer in a gap between the substrate and the semiconductor chip; first bumps connecting the first wires and the semiconductor chip; second bumps connecting the second wires and the semiconductor chip; and