US-20260130238-A1 - SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME

US20260130238A1US 20260130238 A1US20260130238 A1US 20260130238A1US-20260130238-A1

Abstract

There is provided a semiconductor package having improved reliability. The semiconductor package comprising, a first package including a first package substrate and a first semiconductor chip mounted on the first package substrate, an interposer substrate on the first package, a second package including a second package substrate on the interposer substrate, and the second package substrate including a first surface and a second surface opposite to each other, a plurality of solder balls attached onto the first surface of the second package substrate, and the plurality of solder balls connecting the second package substrate and the interposer substrate, and a second semiconductor chip mounted on the second surface of the second package substrate, and a second capacitor between the interposer substrate and the second package substrate, the second capacitor mounted on the interposer substrate and electrically connected to the second semiconductor chip.

Inventors

Gi Tae PARK
Jong Bo Shim

Assignees

SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date: 20260507
Application Date: 20250626
Priority Date: 20241107

Claims (20)

1 . A semiconductor package comprising: a first package including a first package substrate and a first semiconductor chip mounted on the first package substrate; an interposer substrate on the first package; a second package including a second package substrate on the interposer substrate, the second package substrate including, a first surface and a second surface opposite to each other, a plurality of solder balls attached onto the first surface of the second package substrate, the plurality of solder balls connecting the second package substrate and the interposer substrate, and a second semiconductor chip mounted on the second surface of the second package substrate; and a second capacitor between the interposer substrate and the second package substrate, the second capacitor mounted on the interposer substrate and electrically connected to the second semiconductor chip.
2 . The semiconductor package of claim 1 , wherein the first package further includes a plurality of connecting structures connecting the first package substrate and the interposer substrate, and the plurality of solder balls include a first solder ball electrically connected to the plurality of connecting structures and a second solder ball electrically connected to the second capacitor.
3 . The semiconductor package of claim 2 , wherein a separation distance between adjacent first solder balls of the plurality of solder balls is different from a separation distance between the first solder ball and the second solder ball adjacent to each other.
4 . The semiconductor package of claim 3 , wherein the separation distance between the adjacent first solder balls of the plurality of solder balls is smaller than the separation distance between the first solder ball and the second solder ball adjacent to each other.
5 . The semiconductor package of claim 2 , wherein the interposer substrate includes an upper wiring connecting the second capacitor and the second solder ball.
6 . The semiconductor package of claim 1 , wherein the second capacitor is not mounted on the second surface of the second package substrate.
7 . The semiconductor package of claim 1 , wherein a height of the second capacitor is smaller than a height of the plurality of solder balls.
8 . The semiconductor package of claim 1 , further comprising: a first capacitor on the first package substrate and electrically connected to the first semiconductor chip, wherein the first package substrate includes a third surface and a fourth surface opposite to each other, the first capacitor is mounted on the third surface of the first package substrate, and the first semiconductor chip is mounted on the fourth surface of the first package substrate.
9 . The semiconductor package of claim 8 , wherein a width of the second capacitor is greater than a width of the first capacitor.
10 . The semiconductor package of claim 1 , wherein the first semiconductor chip is a logic semiconductor chip, and the second semiconductor chip is a memory semiconductor chip.
11 . A semiconductor package comprising: a first package including a first package substrate and a first semiconductor chip mounted on the first package substrate; an interposer substrate on the first package, the interposer substrate extending in a first direction and a second direction, and including an internal area and a ball area surrounding the internal area; a second package including, a plurality of first solder balls on the ball area, a plurality of second solder balls on the internal area, a second package substrate on the plurality of first solder balls and the plurality of second solder balls, and a second semiconductor chip mounted on the second package substrate; and a second capacitor on the internal area of the interposer substrate, the second capacitor mounted on the interposer substrate, and electrically connected to the second semiconductor chip through the plurality of second solder balls.
12 . The semiconductor package of claim 11 , wherein the first package further includes a plurality of connecting structures connecting the first package substrate and the interposer substrate, and a first solder ball of the plurality of first solder balls is electrically connected to a connecting structure of the plurality of connecting structures.
13 . The semiconductor package of claim 11 , wherein a separation distance between adjacent first solder balls of the plurality of first solder balls is different from a separation distance between a first solder ball and a second solder ball adjacent to each other.
14 . The semiconductor package of claim 13 , wherein the separation distance between the adjacent first solder balls of the plurality of first solder balls is smaller than the separation distance between the first solder ball and the second solder ball adjacent to each other.
15 . The semiconductor package of claim 11 , wherein the second capacitor is not mounted on the second package substrate.
16 . The semiconductor package of claim 11 , further comprising: a first capacitor mounted on the first package substrate and electrically connected to the first semiconductor chip.
17 . The semiconductor package of claim 11 , wherein the first semiconductor chip is a logic semiconductor chip, and the second semiconductor chip is a memory semiconductor chip.
18 . A method for fabricating a semiconductor package, the method comprising: providing a first package substrate; mounting a first semiconductor chip on the first package substrate; disposing an interposer substrate on the first semiconductor chip, the interposer substrate being electrically connected to the first package substrate; mounting a capacitor on the interposer substrate; and disposing a second package on the capacitor, wherein the second package includes a second package substrate electrically connected to the interposer substrate and a second semiconductor chip mounted on the second package substrate, the second semiconductor chip being electrically connected to the capacitor.
19 . The method for fabricating a semiconductor package of claim 18 , wherein the disposing of the second package on the capacitor includes bonding a plurality of solder balls to the interposer substrate, the plurality of solder balls being attached onto the second package substrate, and the plurality of solder balls include first solder balls electrically connected to the first package substrate and second solder balls electrically connected to the capacitor.
20 . The method for fabricating a semiconductor package of claim 18 , wherein the disposing of the interposer substrate on the first package substrate includes forming a connecting structure connecting the first package substrate and the interposer substrate.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims priority from Korean Patent Application No. 10-2024-0156894 filed on Nov. 7, 2024 in the Korean Intellectual Property Office, and all the benefits accruing therefrom under 35 U.S.C. 119, the contents of which in its entirety are herein incorporated by reference. BACKGROUND Some example embodiments of inventive concepts relate to a semiconductor package and a method for fabricating the same. In response to the rapid development of the electronics industry and user's demands, electronic devices are gradually becoming smaller, multifunctional, and larger in capacity, and accordingly, semiconductor packages including a plurality of semiconductor chips may be beneficial. In order to satisfy some industrial requirements, packaging processes of various methods have been developed. An interposer is an electrical interface that routes connections inside one package and/or between different packages from each other. A purpose of the interposer may be to spread a pitch of the wiring to a wider pitch and/or to reroute the connection to another connection. As a representative technology using such an interposer, there is an IPOP (Interposer Package on Package) which may provide a different semiconductor package on a semiconductor package. SUMMARY Some example embodiments of inventive concepts provide a semiconductor package having improved reliability. Alternatively or additionally, some example embodiments of inventive concepts provide a method for fabricating a semiconductor package having improved reliability. However, aspects of the present inventive concepts are not restricted to the example embodiments set forth herein. The above and other aspects of the present inventive concepts will become more apparent to one of ordinary skill in the art to which the example embodiments pertain by referencing the detailed description given below. Some example embodiments of inventive concepts include a semiconductor package comprising, a first package including a first package substrate and a first semiconductor chip mounted on the first package substrate, an interposer substrate on the first package, a second package including a second package substrate on the interposer substrate, and the second package substrate including a first surface and a second surface opposite to each other, a plurality of solder balls attached onto the first surface of the second package substrate, and the plurality of solder balls connecting the second package substrate and the interposer substrate, and a second semiconductor chip mounted on the second surface of the second package substrate, and a second capacitor between the interposer substrate and the second package substrate, the second capacitor mounted on the interposer substrate, and electrically connected to the second semiconductor chip. Some example embodiments of inventive concepts include a semiconductor package comprising, a first package including a first package substrate and a first semiconductor chip mounted on the first package substrate, an interposer substrate on the first package, the interposer substrate extending in a first direction and a second direction, and including an internal area and a ball area surrounding the internal area, a second package including a plurality of first solder balls on the ball area, a plurality of second solder balls on the internal area, a second package substrate on the plurality of first solder balls and the plurality of second solder balls, and a second semiconductor chip mounted on the second package substrate, and a second capacitor on the internal area of the interposer substrate, the second capacitor mounted on the interposer substrate, and electrically connected to the second semiconductor chip through the second solder balls. Some example embodiments of inventive concepts include a method for fabricating a semiconductor package, the method comprising, providing a first package substrate, mounting a first semiconductor chip on the first package substrate, disposing an interposer substrate on the first semiconductor chip, the interposer substrate being electrically connected to the first package substrate, mounting a capacitor on the interposer substrate, and disposing a second package on the capacitor, wherein the second package includes a second package substrate electrically connected to the interposer substrate and a second semiconductor chip mounted on the second package substrate, and the second semiconductor chip being electrically connected to the capacitor. Some example embodiments of inventive concepts include a semiconductor package comprising a first package including a first package substrate, a first semiconductor ship, and a first capacitor, a second package on the first package, the second package including a second package substrate and a second semiconductor chip, the second package being spaced apart from the first package in a first direction, a second capa