US-20260130239-A1 - PACKAGING FOR SEMICONDUCTOR DEVICES FOR HIGH PERFORMANCE COMPUTING APPLICATIONS AND METHODS FOR FORMING THE SAME

Abstract

A semiconductor device and methods of forming the same. In some embodiments, a method for forming a semiconductor device includes forming a redistribution layer that includes connecting vias and a surface mount pad via and the top surface width of each via is larger than a bottom surface width. The method includes connecting a component to the redistribution layer by a plurality of μ-bumps and filling a gap between the component and the redistribution layer with a mold and an underfill. The method includes etching back the redistribution layer to expose the surface mount pad via and attaching a surface mount pad to the surface mount pad via. The surface mount pad is connected to the bottom surface width of the surface mount pad via and the surface mount pad includes a protrude. The method includes connecting a device to a bottom surface of the surface mount pad.

Inventors

• Hsin-Yu Chen
• Meng-Wei Chou
• Yu-Ting Chen
• Yu-Hsiang Hu
• Chien-Hsun Lee

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

Dates

Publication Date

20260507

Application Date

20241101

Claims (20)

1. 1 . A method of forming a semiconductor structure, comprising: forming a redistribution layer, wherein the redistribution layer includes a plurality of vias, wherein the plurality of vias comprise connecting vias and at least one surface mount pad via, wherein a top surface width of each via of the plurality of vias is larger than a bottom surface width of each via of the plurality of vias; etching back the redistribution layer to expose at least a portion of the at least one surface mount pad via; attaching a surface mount pad to each of the at least one surface mount pad via, wherein the surface mount pad is connected to a bottom surface of the surface mount pad via and the surface mount pad includes a protrusion.
2. 2 . The method of claim 1 , wherein forming the redistribution layer further comprises: etching a dielectric material layer to form a surface mount pad cavity; forming a pillar formed of a conductive material in the surface mount pad cavity; depositing a seed layer surrounding the pillar and a surface of the surface mount pad cavity; and forming the conductive material in the surface mount pad cavity to form the surface mount pad via.
3. 3 . The method of claim 2 , wherein forming the redistribution layer further comprises forming a metal trace above the surface mount pad via.
4. 4 . The method of claim 1 , wherein forming the redistribution layer further comprises: etching in a dielectric material layer to form a connecting via cavity; depositing a seed layer on a surface of the connecting via cavity; and forming a conductive material in the connecting via cavity to form the connecting via.
5. 5 . The method of claim 4 , wherein forming the redistribution layer further comprises forming a metal trace above the connecting via.
6. 6 . The method of claim 1 , further comprising attaching a thermal module above the plurality of components.
7. 7 . The method of claim 1 , wherein forming the redistribution layer comprises forming at least six layers, wherein each layer includes at least one of a metal trace or a via.
8. 8 . The method of claim 1 , wherein etching back the dielectric layer exposes a portion of a surface mount pad via, wherein the surface mount pad via has a top surface width that is larger than a bottom surface width.
9. 9 . The method of claim 1 , further comprising depositing a surface mount pad seed layer partially in contact with a surface mount pad via seed layer.
10. 10 . The method of claim 1 , wherein etching back the dielectric layer removes at most 10 μm of a height of the dielectric layer.
11. 11 . A method of forming a pillar within a via comprising: etching a dielectric material layer to form a cavity; forming a pillar formed of a conductive material in the cavity; and forming a conductive material in the cavity to form a via.
12. 12 . The method of claim 11 , further comprising depositing a seed layer surrounding the pillar and a surface of the cavity.
13. 13 . A semiconductor structure, comprising: a surface mount pad, wherein the surface mount pad includes a pad and a plating, wherein the pad is in contact with the bottom width of the via and has a protrusion; and a seed layer located above the surface mount pad and partially in contact with a via seed layer.
14. 14 . The semiconductor structure of claim 13 , further comprising a redistribution layer comprising a via and a metal trace located within a dielectric material, wherein the via is formed below the metal trace, a top surface width of the via is larger than a bottom surface width of the via, a pillar located in the via surrounded by a pillar seed layer, and the via is lined with the via seed layer and filled with a conductive material.
15. 15 . The semiconductor structure of claim 14 , wherein the redistribution layer further comprises a connecting via, wherein the connecting via has a top surface width that is larger than a bottom surface width.
16. 16 . The semiconductor structure of claim 14 , further comprising a plurality of μ-bumps, wherein each μ-bump connects a component of the plurality of components to a connecting via in the redistribution layer and the μ-bumps have a pitch of at most 150 μm.
17. 17 . The semiconductor structure of claim 16 , further comprising: an underfill layer, wherein the underfill layer is located between the plurality of components and the redistribution layer and surrounds the μ-bumps; and a mold layer, wherein the mold layer surrounds each side and a top of the underfill layer and forms a sidewall.
18. 18 . The semiconductor structure of claim 13 , wherein the pad is formed of copper and the plating is formed of a tin alloy.
19. 19 . The semiconductor structure of claim 13 , wherein the dielectric material includes a plurality of dielectric layers and each dielectric layer includes at least one connecting via, at least one surface mount pad via, or at least one metal trace.
20. 20 . The semiconductor structure of claim 13 , further comprising: a plurality of components including at least one high-bandwidth memory component; at least one device, wherein the device is attached to a bottom surface of the surface mount pad; and a thermal module located above the plurality of components.

Description

BACKGROUND The semiconductor industry has continually grown due to continuous improvements in integration density of various electronic components, e.g., transistors, diodes, resistors, capacitors, etc. For the most part, these improvements in integration density have come from successive reductions in minimum feature size, which allows more components to be integrated into a given area (i.e., footprint). Packaging substrates are used as structures for attaching semiconductor dies to a printed circuit board. A semiconductor package may include one or more semiconductor devices (e.g., semiconductor dies, interposer modules, etc.) mounted on a substrate. For example, in wafer-scale heterogeneous integration devices, various different semiconductor materials, such as processing units, are used on a single carrier, such as a wafer, to enable advanced modern computing applications. Wafer-scale heterogeneous integration devices provide powerful systems with diverse functionalities, such as high performance computing and artificial intelligence. While heterogeneous integrated devices provide high-speed applications, such as artificial intelligence, multiple challenges exist. For example, wafer-scale heterogeneous integration devices face challenges with yields and defects, material compatibility, thermal management, and bond alignment and strength. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of this disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1A is an example schematic of a vertical cross-sectional view of forming an initial layer of the redistribution layer and a blown-up view of a surface mount pad via according to various embodiments of the present disclosure. FIG. 1B is an example schematic of a vertical cross-sectional view of forming a secondary layer of the redistribution layer and a blown-up view of a surface mount pad via according to various embodiments of the present disclosure. FIG. 1C is an example schematic of a vertical cross-sectional view of a redistribution layer and a blown-up view of a connecting via according to various embodiments of the present disclosure. FIG. 2A is an example schematic of a vertical cross-sectional view of bonding the redistribution layer to a carrier according to various embodiments of the present disclosure. FIG. 2B is an example schematic of a vertical cross-sectional view of connecting components to the redistribution layer using microbumps (μ-bumps) and a blown-up view of a μ-bump according to various embodiments of the present disclosure. FIG. 2C is an example schematic of a vertical cross-sectional view of forming an underfill layer and a mold layer according to various embodiments of the present disclosure. FIG. 2D is an example schematic of a vertical cross-sectional view of debonding and bonding various carriers according to various embodiments of the present disclosure. FIG. 2E is an example schematic of a vertical cross-sectional view of forming surface mount pads with a blown-up view of a surface mount pad of a ball grid array (BGA) according to various embodiments of the present disclosure. FIG. 2F is an example schematic of a vertical cross-sectional view of applying grind tape to the BGA to protect the BGA during subsequent grinding and cleaning processes according to various embodiments of the present disclosure. FIG. 2G is an example schematic of a vertical cross-sectional view of a drilling and cleaning process according to various embodiments of the present disclosure. FIG. 2H is an example schematic of a vertical cross-sectional view of connecting devices to the surface mount pads according to various embodiments of the present disclosure. FIG. 2I is an example schematic of a vertical cross-sectional view of attaching a thermal module according to various embodiments of the present disclosure. FIG. 3 is an example schematic of a top-view of a semiconductor device according to various embodiments of the present disclosure. FIG. 4 is an example flowchart illustrating a method of forming a semiconductor device according to an embodiment of the present disclosure. FIG. 5 is an example flowchart illustrating a method of forming a surface mount pad according to an embodiment of the present disclosure. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodi