US-20260130241-A1 - PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

US20260130241A1US 20260130241 A1US20260130241 A1US 20260130241A1US-20260130241-A1

Abstract

Provided is a package structure, which includes a substrate, an interposer module, and a chip module. The interposer module is disposed on the substrate. The interposer module includes a first insulating layer, a second insulating layer, and multiple dummy terminals. The first insulating layer is disposed between the second insulating layer and the substrate. The multiple dummy terminals are in direct contact with the first insulating layer and the substrate. The chip module is disposed on the interposer module and is electrically connected to the substrate through the interposer module. Also provided is a manufacturing method of a package structure. The plurality of external terminals include a plurality of functional components. The substrate is disposed between the plurality of dummy terminals and the plurality of external terminals, and the plurality of dummy terminals are electrically insulated the plurality of functional components.

Inventors

Shang-Yu Chang Chien
Yi-Kai FU

Assignees

POWERTECH TECHNOLOGY INC.

Dates

Publication Date: 20260507
Application Date: 20251017
Priority Date: 20241106

Claims (18)

1 . A package structure, comprising: a substrate; an interposer module, disposed on the substrate, wherein: the interposer module comprises a first insulating layer, a second insulating layer, and a plurality of dummy terminals; the first insulating layer is disposed between the second insulating layer and the substrate; and the plurality of dummy terminals are in direct contact with the first insulating layer and the substrate; and a chip module, disposed on the interposer module and electrically connected to the substrate through the interposer module; and a plurality of external terminals, comprising a plurality of functional components, wherein the substrate is disposed between the plurality of dummy terminals and the plurality of external terminals, and the plurality of dummy terminals are electrically insulated the plurality of functional components.
2 . The package structure according to claim 1 , wherein the interposer module further comprises a plurality of bridge dies that are disposed on the first insulating layer through an adhesive layer, the second insulating layer encapsulates the plurality of bridge dies, and the plurality of dummy terminals correspond to the plurality of bridge dies in a stacking direction of the substrate, the interposer module and the chip module.
3 . The package structure according to claim 2 , wherein orthographic projections of the plurality of dummy terminals on the substrate overlap with orthographic projections of the plurality of bridge dies on the substrate.
4 . The package structure according to claim 2 , wherein the adhesive layer and the plurality of dummy terminals are respectively in direct contact with opposite surfaces of the first insulating layer.
5 . The package structure according to claim 2 , wherein the interposer module comprises a redistribution layer structure, the first insulating layer is a bottom insulating layer of the redistribution layer structure, and the adhesive layer is in direct contact with a top insulating layer in the redistribution layer structure relative to the first insulating layer.
6 . The package structure according to claim 1 , wherein the plurality of dummy terminals are in direct contact with a dummy pad of a top part of the substrate.
7 . The package structure according to claim 1 , wherein the external terminals further comprising a plurality of dummy components, wherein t the plurality of dummy terminals are coupled to the plurality of dummy components.
8 . The package structure according to claim 1 , further comprising a plurality of conductive terminals, wherein the plurality of conductive terminals are disposed between the interposer module and the substrate and surround the plurality of dummy terminals.
9 . The package structure according to claim 1 , further comprising a cover that is disposed on the substrate, wherein there is a thermal interface material between the cover and each of a plurality of chiplets in the chip module.
10 . The package structure according to claim 9 , wherein the plurality of chiplets in the chip module have different heights.
11 . The package structure according to claim 10 , wherein there is a thermal interface material with a different thickness between the cover and each of the plurality of chiplets in the chip module.
12 . A manufacturing method of a package structure, comprising: providing a substrate; providing an interposer module, wherein the interposer module is singulated and comprises a plurality of dummy terminals; disposing the interposer module on the substrate through the plurality of dummy terminals; providing a chip module; and disposing the chip module on the interposer module, wherein the chip module is electrically connected to the substrate through the interposer module.
13 . The manufacturing method according to claim 12 , wherein after the chip module is disposed on the interposer module, an encapsulating process and a singulation process are not performed.
14 . The manufacturing method according to claim 12 , further comprising: bonding the interposer module and the substrate through a plurality of first conductive terminals; bonding the chip module and the interposer module through a plurality of second conductive terminals; and cladding the plurality of first conductive terminals and the plurality of second conductive terminals respectively through a first protective member and a second protective member.
15 . The manufacturing method according to claim 14 , wherein the first protective member and the second protective member are respectively formed through performing a dispensing process or a film sticking process.
16 . The manufacturing method according to claim 14 , wherein the first protective member and the second protective member are formed in different processes.
17 . The manufacturing method according to claim 12 , wherein steps of forming the interposer module comprise: providing a first insulating layer; disposing a plurality of bridge dies on the first insulating layer; forming a second insulating layer and encapsulating the plurality of bridge dies; forming the plurality of dummy terminals on the first insulating layer; and performing a singulation process.
18 . The manufacturing method according to claim 17 , further comprising forming a plurality of conductive terminals to surround the plurality of dummy terminals.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims the priority benefit of Taiwan application serial no. 113142461, filed on Nov. 6, 2024. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of the disclosure. BACKGROUND Technical Field The disclosure relates to a package structure and a manufacturing method thereof. Description of Related Art With the advancement of technology, the requirements for electronic products in the market are also increasing day by day. For example, how to ensure that the package structure has good quality has become a current topic of research. SUMMARY The disclosure provides a package structure and a manufacturing method thereof, of which a yield is effectively improved, ensuring good quality. A package structure of the disclosure includes a substrate, an interposer module, a chip module, and a plurality of external terminals. The interposer module is disposed on the substrate. The interposer module includes a first insulating layer, a second insulating layer, and multiple dummy terminals. The first insulating layer is disposed between the second insulating layer and the substrate. The multiple dummy terminals are in direct contact with the first insulating layer and the substrate. The chip module is disposed on the interposer module and is electrically connected to the substrate through the interposer module. The plurality of external terminals include a plurality of functional components. The substrate is disposed between the plurality of dummy terminals and the plurality of external terminals, and the plurality of dummy terminals are electrically insulated the plurality of functional components. A manufacturing method of a package structure of the disclosure at least includes: a substrate is provided; an interposer module including multiple dummy terminals is provided; the interposer module is disposed on the substrate through multiple dummy terminals; a chip module is provided; and the chip module is disposed on the interposer module, the interposer module is singulated, and the chip module is electrically connected to the substrate through the interposer module. Based on the above, since the number of processes that the chip module goes through may be decreased, the risk of yield loss in the process may be reduced, and at the same time, the stress in the process may be disperse by the design of dummy terminals. Accordingly, the yield of the package structure of the disclosure is effectively improved, thereby ensuring good quality. In order to make the features and advantages of the disclosure more comprehensible, the following examples are given and described in detail with the accompanying drawings as follows. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1G are partial cross-sectional schematic diagrams of parts of a manufacturing method of a package structure according to an embodiment of the disclosure. FIG. 2, FIG. 3, FIG. 4, FIG. 5, FIG. 6, FIG. 7, and FIG. 8 are partial cross-sectional schematic diagrams of a package structure according to some embodiments of the disclosure. DESCRIPTION OF THE EMBODIMENTS Directional terms used herein (such as up, down, right, left, front, back, top, bottom) are only used with reference to the drawings and are not intended to imply absolute orientation. Unless expressly stated otherwise, any method described herein is in no way intended to be construed as requiring that the steps are to be performed in a particular order. The disclosure will be described more fully with reference to the drawings of the embodiment. However, the disclosure may also be embodied in various forms and should not be limited to the embodiments described herein. The thickness, dimension, or size of layers or regions in the drawings are exaggerated for clarity. The same or similar reference numerals indicate the same or similar components, and will not be repeated one by one in the following paragraphs. It will be understood that, although the terms “first”, “second”, “third”, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Unless otherwise stated, the term “between” used to define numerical ranges in the disclosure is intended to cover a range equal to and between the endpoint values. For example, the dimension range is between the first value and the second value, which means that the dimension range may cover the first value, the second value and any value between the first value and the second value. FIG. 1A to FIG. 1G are partial cross-sectional schematic diagrams of parts of a manufacturing method of a package structure according to an embodiment of the disclosure. Please refer to FIG