US-20260130242-A1 - SEMICONDUCTOR PACKAGING WITH EMBEDDED DEVICE AND REDISTRIBUTION LAYER

Abstract

A semiconductor package may include a semiconductor die disposed on a first substrate and having at least a first contact on a first side and at least a second contact on a second side that is opposed to the first side. An insulator, such as a dielectric, may encapsulate the semiconductor die. A second substrate may be disposed on the first substrate with the semiconductor die therebetween. Either of the first or second substrate may have a cavity formed therein, and the semiconductor die may be disposed in one or both of the cavities. Vias through the first substrate, the dielectric, and/or the second substrate may be used to connect to the semiconductor die, enabling formation of a redistribution layer. Magnetic elements and associated windings may also be used in place of the semiconductor die and associated contacts.

Inventors

• Dinesh Ramanathan
• Anders Soren Lind
• Vijay B. Rentala
• Christopher Lee Tessler
• Michael J. Seddon
• Gabrielle Robert
• Jorge Lubguban

Assignees

• SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Dates

Publication Date

20260507

Application Date

20251031

Claims (20)

1. 1 . A semiconductor package, comprising: a substrate; a semiconductor die disposed on the substrate and having at least a first contact on a first side and at least a second contact on a second side that is opposed to the first side; a dielectric encapsulant encapsulating the semiconductor die and having vias formed therein; and a redistribution layer formed on the dielectric encapsulant and connected to the first contact and the second contact through the vias.
2. 2 . The semiconductor package of claim 1 , further comprising a conductive layer electrically connected to the second contact and disposed between the second contact and the substrate, wherein the conductive layer is electrically connected to the redistribution layer through at least one of the vias.
3. 3 . The semiconductor package of claim 1 , further comprising a cavity formed in the substrate, wherein the semiconductor die is disposed within the cavity.
4. 4 . The semiconductor package of claim 1 , further comprising: a second substrate formed of semiconductor material and disposed on the dielectric encapsulant, the second substrate having second vias formed therein, wherein the redistribution layer is formed on the second substrate and connected to the first contact and the second contact through the vias and the second vias.
5. 5 . The semiconductor package of claim 1 , further comprising: a second semiconductor die disposed on the redistribution layer; a second dielectric encapsulant formed on the redistribution layer and encapsulating the second semiconductor die, the second dielectric encapsulant having second vias formed therein; and a second redistribution layer formed on the second dielectric encapsulant and connected to the semiconductor die through the vias and the second vias, and connected to the second semiconductor die through the second vias.
6. 6 . The semiconductor package of claim 1 , further comprising: a second substrate formed of semiconductor material; a second semiconductor die disposed on a first side of the second substrate facing the semiconductor die; a second dielectric encapsulant at least partially encapsulating the second semiconductor die; second vias formed through the second dielectric encapsulant, with the semiconductor die and the second semiconductor die connecting through the second vias; third vias formed through the second dielectric encapsulant and through the second substrate; fourth vias formed through the second substrate; and a second redistribution layer formed at least partially on a second side of the second substrate, opposed to the first side of the second substrate, and connected to the redistribution layer and the second semiconductor die through the second vias, the third vias, and the fourth vias.
7. 7 . The semiconductor package of claim 1 , further comprising: a second substrate having a cavity formed therein, wherein the substrate is positioned within the cavity.
8. 8 . A semiconductor package comprising: a first substrate; a semiconductor die disposed on the first substrate; a second substrate having a cavity formed therein, the cavity defining a first portion of the second substrate having a first depth and a second portion of the second substrate having a second depth that is greater than the first depth, and the second substrate being attached to the first substrate by the second portion of the second substrate and with the semiconductor die disposed within the cavity; a via formed through the first portion of the second substrate; and a contact disposed on the second substrate and electrically connected to the semiconductor die through the via.
9. 9 . The semiconductor package of claim 8 , wherein the via is a second via, the contact is a second contact, and further comprising: a first via formed through the first substrate; and a first contact disposed on the first substrate and electrically connected to the semiconductor die through the first via.
10. 10 . The semiconductor package of claim 8 , further comprising: a second via formed through the second portion of the second substrate; a metal layer formed between the semiconductor die and the first substrate and extending between the first substrate and the second portion of the second substrate; and a redistribution layer formed on the second substrate that includes the contact and a second contact electrically connected to the metal layer through the second via.
11. 11 . The semiconductor package of claim 8 , wherein the cavity is a second cavity, and further comprising: a first cavity formed in the first substrate and aligned with the second cavity to form a combined cavity, wherein the semiconductor die is disposed within the combined cavity.
12. 12 . The semiconductor package of claim 8 , further comprising: a first metal attachment point between the first substrate and the second substrate; a second metal attachment point between the semiconductor die and the second substrate; and a third metal attachment point between the semiconductor die and the first substrate.
13. 13 . The semiconductor package of claim 8 , further comprising: a first metal layer extending through the first substrate and parallel to a surface of the semiconductor die, and electrically connected to the semiconductor die; a second metal layer that includes the contact and that extends through the second substrate and parallel to the surface of the semiconductor die; a second via formed through the second portion of the second substrate; a third via formed through the first substrate; and a redistribution layer formed on the first substrate between the first substrate and the second substrate, electrically connected to the first metal layer by way of the third via and to the second metal layer by way of the second via.
14. 14 . The semiconductor package of claim 8 , wherein the second substrate includes a semiconductor substrate, and further comprising an electronic element formed in the second substrate and connected to the semiconductor die by way of the contact.
15. 15 . The semiconductor package of claim 8 , wherein at least one of the first substrate and the second substrate includes a semiconductor substrate, and further comprising micro-electronic mechanical systems element formed in at least one of the first substrate and the second substrate and connected to the semiconductor die by way of the contact.
16. 16 . The semiconductor package of claim 15 , wherein the semiconductor die and the micro-electronic mechanical systems element are combined to provide a relay.
17. 17 . A semiconductor package, comprising: a substrate having a cavity formed therein; a magnetic element disposed in the cavity; a metallic winding disposed on the substrate and surrounding the magnetic element; a dielectric encapsulant encapsulating the magnetic element and the metallic winding; and a contact electrically connected to the metallic winding through a via formed in the dielectric encapsulant.
18. 18 . The semiconductor package of claim 17 , wherein the magnetic element includes a cylindrical ferrous puck.
19. 19 . The semiconductor package of claim 17 , wherein the metallic winding comprises patterned metal layers that coil around the magnetic element in at least two turns.
20. 20 . The semiconductor package of claim 17 , wherein the metallic winding has an inner terminal proximate an edge of the magnetic element and spiral to an outer terminal distal from the magnetic element.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims the benefit of and priority to U.S. Provisional Application No. 63/715,912, filed Nov. 4, 2024, and U.S. Provisional Application No. 63/736,415, filed Dec. 19, 2024, and to U.S. Non-provisional Application xx/xxx, xxx, filed concurrently herewith and titled SEMICONDUCTOR MODULE WITH POWER BRIDGE FOR INTEGRATED DIE INTERCONNECTION, which are incorporated by reference herein in their entireties. TECHNICAL FIELD This description relates to semiconductor device packaging. BACKGROUND Conventional packaging techniques for semiconductor devices have a number of shortcomings. Such shortcomings are particularly problematic in the context of packaging semiconductor power devices, because such devices typically have multiple requirements that must be met concurrently by a selected packaging technique. For example, semiconductor power devices often require high-voltage and high temperature operation, thereby requiring high-voltage isolation for safety reasons and high thermal conductivity for heat transfer to a heatsink(s) of some type. Power device packaging is also often desired to be low cost and small size, further exacerbating difficulties in meeting voltage/thermal requirements. In a specific example, it is desirable to provide semiconductor modules for traction inverters for electric vehicles with a low on-resistance across many parallel devices, along with low circuit parasitics, while maintaining the above-referenced requirements for low cost, small size, and voltage/thermal management. In another specific example, artificial intelligence (AI) datacenters have large-scale power requirements, but current packaging techniques suffer from, e.g., complexity associated with multi-chip packaging within a small footprint (exacerbated by the use of flip-chip technology), poor thermal conductivity of mold compounds used for encapsulation, and undesirably large package volume caused by the inclusion of bond wires. More recent approaches attempt to address the above and related challenges, such as approaches using printed circuit board (PCB) embedding. However, these approaches can be expensive and complex, while still failing to satisfactorily address existing challenges. For example, PCB embedding typically requires expensive laser drilling for vias, while providing insufficient cooling. SUMMARY According to one general aspect, a semiconductor package includes a substrate, a semiconductor die disposed on the substrate and having at least a first contact on a first side and at least a second contact on a second side that is opposed to the first side, a dielectric encapsulant encapsulating the semiconductor die and having vias formed therein, and a redistribution layer formed on the dielectric encapsulant and connected to the first contact and the second contact through the vias. According to another general aspect, a method of making a semiconductor package includes providing a semiconductor die on a substrate, the semiconductor die having at least a first contact on a first side and at least a second contact on a second side that is opposed to the first side, encapsulating the semiconductor die with a dielectric encapsulant, forming vias in the dielectric encapsulant, and forming a redistribution layer on the dielectric encapsulant that is connected to the first contact and the second contact through the vias. According to another general aspect, a semiconductor package includes a first substrate, a semiconductor die disposed on the first substrate, a second substrate having a cavity formed therein, the cavity defining a first portion of the second substrate having a first depth and a second portion of the second substrate having a second depth that is greater than the first depth, and the second substrate being attached to the first substrate by the second portion of the second substrate and with the semiconductor die disposed within the cavity, a via formed through the first portion of the second substrate, and a contact disposed on the second substrate and electrically connected to the semiconductor die through the via. According to another general aspect, a method of making a semiconductor package includes disposing a semiconductor die on a first substrate, forming a cavity in a second substrate, the cavity defining a first portion of the second substrate having a first depth and a second portion of the second substrate having a second depth that is greater than the first depth, attaching the second substrate to the first substrate by the second portion of the second substrate and with the semiconductor die disposed within the cavity, forming a via through the first portion of the second substrate, and disposing a contact on the second substrate and electrically connected to the semiconductor die through the via. According to another general aspect, a semiconductor package includes a substrate having a cavity formed therein, a magnetic element disposed