US-20260130243-A1 - SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Abstract

A semiconductor device includes a substrate, a first die embedded in the substrate, a plurality of first connectors located between and electrically connected to the first die and the substrate. a second die bonded to a first surface of the substrate, a third die bonded to the first surface of the substrate, an encapsulant encapsulating the second die and the third die, and a plurality of second connectors located on a second surface opposite to the first surface of the substrate.

Inventors

• Xuewen Tang
• Ji-Feng Ying
• Wen-Hsien Chuang
• Yao-Chun Chuang

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
• TSMC Arizona Corporation

Dates

Publication Date

20260507

Application Date

20241105

Claims (20)

1. 1 . A semiconductor device, comprising: a substrate; a first die, embedded in the substrate; a plurality of first connectors, located between and electrically connected to the first die and the substrate; a second die, bonded to a first surface of the substrate; a third die, bonded to the first surface of the substrate; an encapsulant, encapsulating the second die and the third die; and a plurality of second connectors, located on a second surface opposite to the first surface of the substrate.
2. 2 . The semiconductor device as claimed in claim 1 , wherein the substrate comprises a first conductive feature and a second conductive feature, the first die is located between the first conductive feature and the second conductive feature, the first conductive feature is connected to a first surface of the first die and the plurality of first connectors are connected to a second surface opposite to the first surface of the first die.
3. 3 . The semiconductor device as claimed in claim 1 , wherein the first die comprises an interconnect structure and a plurality of through vias, the plurality of through vias are located between the interconnect structure and the plurality of first connectors, and the plurality of through vias extend from the interconnect structure to the plurality of first connectors.
4. 4 . The semiconductor device as claimed in claim 3 , wherein the interconnect structure comprises a first portion and a pair of second portions, the first portion is isolated from the plurality of through vias, and the pair of second portions are electrically connected to the plurality of through vias.
5. 5 . The semiconductor device as claimed in claim 4 , wherein the second die and the third die are electrically connected to each other through the first portion.
6. 6 . The semiconductor device as claimed in claim 1 , wherein the plurality of second connectors comprises a plurality of signal terminals electrically connected to the first die through the plurality of first connectors.
7. 7 . The semiconductor device as claimed in claim 1 , wherein the substrate comprises: a core layer; a first redistribution structure, located on a first surface of the core layer; and a second redistribution structure, located on a second surface opposite to the first surface of the core layer, wherein the first die is surrounded by the first redistribution structure.
8. 8 . The semiconductor device as claimed in claim 1 , wherein the first die is provided under and connects to the second die and the third die.
9. 9 . A semiconductor device, comprising: a substrate; a first die, embedded in the substrate; a plurality of first connectors, located between and electrically connected to the first die and the substrate; a second die, located on a first surface of the substrate; a third die, located on the first surface of the substrate; an encapsulant, encapsulating the second die and the third die; and a plurality of second connectors, located on a second surface opposite to the first surface of the substrate, wherein a first signal routing between the second die and the plurality of second connectors is provided through one of the plurality of first connectors and the first die, and a second signal routing between the third die and the plurality of second connectors is provided through another one of the plurality of first connectors and the first die.
10. 10 . The semiconductor device as claimed in claim 9 , wherein the first die comprises a base portion, a power portion and a pair of signal portions, the pair of signal portions are penetrated through the base portion, and the power portion is floated in the base portion.
11. 11 . The semiconductor device as claimed in claim 10 , wherein the first signal routing and the second signal routing pass through the pair of signal portions.
12. 12 . The semiconductor device as claimed in claim 10 , wherein each of the pair of signal portions comprises a first interconnect layer and a plurality of through vias, the power portion comprises a second interconnect layer, and the second interconnect layer is spaced from the plurality of through vias.
13. 13 . The semiconductor device as claimed in claim 9 , wherein orthographic projections of the second die and the third die on the substrate covers the first die.
14. 14 . The semiconductor device as claimed in claim 13 , wherein the first die is partially overlapped the second die in a vertical direction and the first die is partially overlapped the third die in the vertical direction.
15. 15 . The semiconductor device as claimed in claim 9 , wherein the first die is inserted between a plurality of conductive features of the substrate.
16. 16 . A manufacturing method of a semiconductor device, comprising: providing a first die; embedding and electrically connected the first die in a substrate by a plurality of first connectors; bonding a second die to a first surface of the substrate; bonding a third die to the first surface of the substrate; encapsulating the second die and the third die by an encapsulant; and forming a plurality of second connectors located on a second surface opposite to the first surface of the substrate, wherein a first signal routing between the second die and the plurality of second connectors and a second signal routing between the third die and the plurality of second connectors are configured by the first die respectively.
17. 17 . The manufacturing method of a semiconductor device as claimed in claim 16 , further comprising: forming an interconnect structure on a base material layer and a plurality of through vias in the base material layer to form the first die.
18. 18 . The manufacturing method of a semiconductor device as claimed in claim 16 , wherein portions of the substrate are formed by a plurality of redistribution processes.
19. 19 . The manufacturing method of a semiconductor device as claimed in claim 18 , wherein a plurality of conductive features formed by the plurality of redistribution processes is configured to surround the first die.
20. 20 . The manufacturing method of a semiconductor device as claimed in claim 16 , wherein the first die is a passive device.

Description

BACKGROUND Semiconductor packages are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. In terms of the packaging used for integrated circuit components or semiconductor dies, one or more dies or packages are generally bonded to a circuit carrier (e.g., a system board, a printed circuit board, or the like) for electrical connections to other external devices or electronic components. To respond to the increasing demand for miniaturization, higher speed and better electrical performance, more creative packaging and assembling techniques are actively researched. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1A to FIG. 1D are cross-sectional view illustrating a method of forming a first die of the semiconductor device according to a first embodiment of the disclosure. FIG. 2A to FIG. 2F are cross-sectional view illustrating a method of forming a semiconductor device according to an embodiment of the disclosure. FIG. 3 is cross-sectional view illustrating a semiconductor device according to another embodiment of the disclosure. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Further, when a number or a range of numbers is described with “about,” “approximate,” and the like, the term is intended to encompass numbers that are within a reasonable range considering variations that inherently arise during manufacturing as understood by one of ordinary skill in the art. For example, the number or range of numbers encompasses a reasonable range including the number described, such as within +/−10% of the number described, based on known manufacturing tolerances associated with manufacturing a feature having a characteristic associated with the number. For example, a material layer having a thickness of “about 5 nm” can encompass a dimension range from 4.25 nm to 5.75 nm where manufacturing tolerances associated with depositing the material layer are known to be +/−15% by one of ordinary skill in the art. Still further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. FIG. 1A to FIG. 1D are cross-sectional view illustrating a method of forming a first die of the semiconductor device according to a first embodiment of the disclosure. FIG. 1A to FIG. 1D are a schematic cross-sectional view illustrating the preparation of a first die for subsequent processes according to the embodiment of the disclosure. FIG. 3 is cross-sectional view illustrating a semiconductor device according to another embodiment of the disclosure. Referring to FIG. 1A, a base material layer 110 is provided, for example, the base material layer 110 is a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, a semiconductor on sapphire substrate, other supporting substrate (e.g., quartz, glass, etc.), combinations thereof, or the