US-20260130245-A1 - MICROELECTRONIC ASSEMBLIES INCLUDING MULTIPLE LINERS IN THROUGH-GLASS VIAS

Abstract

Disclosed herein are microelectronic assemblies and related devices and methods for alleviating stresses in through-glass vias by providing multiple liner materials. In some embodiments, a microelectronic assembly may include a glass core with a via including a first conductive material; a first liner on a sidewall of the via, the first liner including a dielectric material having a width between 0.1 and 100 nanometers; and a second liner between the first liner and the first conductive material, the second liner including a second conductive material having a width between 5 and 20 nanometers. In some embodiments, the first conductive material includes copper and the second conductive material includes ruthenium or copper. In some embodiments, a microelectronic assembly may further include a third liner between the second liner and the first conductive material, the third liner including a third conductive material having a width between 100 and 250 nanometers.

Inventors

• Kihyun Kim
• Darko Grujicic
• Marcel Arlan Wall
• Jeremy Cross
• Shayan Kaviani

Assignees

• INTEL CORPORATION

Dates

Publication Date

20260507

Application Date

20241107

Claims (20)

1. 1 . A microelectronic assembly, comprising: a core including a through-via, wherein the through-via includes a first conductive material having a first average grain size; a first liner material on a sidewall of the through-via, wherein the first liner material includes a dielectric material; and a second liner material between the first liner material and the first conductive material of the through-via, wherein the second liner material includes a second conductive material having a second average grain size, wherein the first average grain size is greater than the second average grain size.
2. 2 . The microelectronic assembly of claim 1 , wherein the first conductive material includes copper and the second liner material includes copper.
3. 3 . The microelectronic assembly of claim 2 , wherein the first average grain size is between 100 nanometers and 2 microns and the second average grain size is between 8 nanometers and 20 nanometers.
4. 4 . The microelectronic assembly of claim 1 , wherein the second liner material has a width between 5 nanometers and 30 nanometers.
5. 5 . The microelectronic assembly of claim 1 , wherein the dielectric material of the first liner material includes silicon and oxygen; silicon and nitrogen; silicon and carbon; silicon, oxygen, and carbon; or silicon, nitrogen, and carbon.
6. 6 . The microelectronic assembly of claim 1 , wherein the first liner material has a width between 0.1 nanometer and 100 nanometers.
7. 7 . The microelectronic assembly of claim 1 , wherein a material of the core includes bulk glass.
8. 8 . The microelectronic assembly of claim 1 , wherein a thickness of the core is between 50 microns and 2 millimeters.
9. 9 . A microelectronic assembly, comprising: a glass layer having a first surface and an opposing second surface; a via extending through the glass layer between the first surface and the second surface, the via including a first conductive material; a first liner material on a sidewall of the via, wherein the first liner material includes a dielectric material having a width between 0.1 nanometer and 100 nanometers; and a second liner material between the first liner material and the first conductive material of the via, wherein the second liner material includes a second conductive material different than the first conductive material and having a width between 5 nanometers and 20 nanometers.
10. 10 . The microelectronic assembly of claim 9 , wherein the first conductive material includes copper and the second conductive material includes ruthenium.
11. 11 . The microelectronic assembly of claim 9 , wherein the dielectric material of the first liner material includes silicon and oxygen; silicon and nitrogen; silicon and carbon; silicon, oxygen, and carbon; or silicon, nitrogen, and carbon.
12. 12 . The microelectronic assembly of claim 9 , wherein the via has an aspect ratio between 5:1 and 30:1.
13. 13 . The microelectronic assembly of claim 9 , further comprising: a third liner material between the second liner material and the first conductive material of the via, wherein the third liner material includes a third conductive material having a width between 100 nanometers and 250 nanometers.
14. 14 . The microelectronic assembly of claim 13 , wherein the third conductive material includes copper having an average grain size between 10 nanometers and 100 nanometers.
15. 15 . The microelectronic assembly of claim 13 , wherein the third conductive material includes ruthenium, zinc, iron, nickel, tin, lead, or silver.
16. 16 . A microelectronic assembly, comprising: a glass core having a first surface and an opposing second surface; a conductive via through the glass core; a first liner in the conductive via, the first liner including a dielectric material; and a second liner in the conductive via between the first liner and a material of the conductive via, the second liner including alternating layers of a first conductive material and a second conductive material, wherein an overall width of the second liner is between 5 nanometers and 30 nanometers.
17. 17 . The microelectronic assembly of claim 16 , wherein the first conductive material includes ruthenium and the second conductive material includes copper.
18. 18 . The microelectronic assembly of claim 16 , wherein the second liner includes between 50 and 300 alternating layers.
19. 19 . The microelectronic assembly of claim 16 , wherein the dielectric material of the first liner includes silicon and oxygen; silicon and nitrogen; silicon and carbon; silicon, oxygen, and carbon; or silicon, nitrogen, and carbon.
20. 20 . The microelectronic assembly of claim 16 , wherein the first liner has a width between 0.1 nanometer and 100 nanometers.

Description

BACKGROUND For the past several decades, scaling of features in integrated circuits (ICs) has been a driving force behind an ever-growing semiconductor industry and emerging applications in fields such as big data, artificial intelligence, mobile communications, and autonomous driving. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows incorporation of an increased number of memory or logic devices on a chip, lending to the fabrication of products with increased capacity. The drive for the ever-increasing capacity, however, is not without issue. The necessity to optimize fabrication and performance of each component (e.g., of each transistor) is becoming increasingly significant. Parallel to optimizations at the transistor level, advanced IC packaging landscape is rapidly evolving to accommodate performance expectations and requirements of shrinking transistor size. Multiple IC dies are now commonly coupled together in a multi-die IC package to integrate features or functionality and to facilitate connections to other components, such as package substrates. For example, IC packages may include an embedded multi-die interconnect bridge (EMIB) for coupling two or more IC dies. Integration of multiple dies in a single IC package has tremendous benefits but adds additional complexities due to placing materials with different material properties in close proximity to one another. When an IC package undergoes multiple processing steps involving various temperatures and pressure loads, individual materials within the package may behave differently from one another, resulting in out of plane deformation of various layers, known as “package warpage.” One way to address package warpage is to use stiffer cores to which different IC dies are attached. Recently, glass cores have been explored as alternatives to organic resin-based cores (e.g., cores based on using Ajinomoto Build-up Film(ABF)). Glass is considered more rigid than organic resin-based materials and has several advantages such as excellent thermal properties, low coefficient of thermal expansion (CTE), high electrical insulation, chemical resistance, optical transparency, and compatibility with advances semiconductor properties. However, a major challenge for widespread adoption of glass cores is the fact that glass is highly susceptible to damage due to mechanical and/or thermal stresses, e.g., damage due to stresses caused by through-glass vias (TGVs) filled with metals. BRIEF DESCRIPTION OF THE DRAWINGS Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings. FIG. 1 is a schematic side, cross-sectional view of an example microelectronic assembly according to some embodiments of the present disclosure. FIG. 2 is a schematic side, cross-sectional view of another example microelectronic assembly according to some embodiments of the present disclosure. FIG. 3 illustrates surfaces of a glass core from which TGV stress may initiate, according to some embodiments of the present disclosure. FIGS. 4A-4C are simplified schematic side, cross-sectional views of example portions of microelectronic assemblies according to some embodiments of the present disclosure. FIGS. 5A-5D are simplified side, cross-sectional views illustrating various manufacturing steps of an example microelectronic assembly according to some embodiments of the present disclosure. FIG. 6 is a flow diagram of an example fabrication method for providing a glass core with multiple liners in one or more TGVs, in accordance with some embodiments of the present disclosure. FIG. 7 is a cross-sectional view of a device package that may include one or more microelectronic assemblies in accordance with any of the embodiments disclosed herein. FIG. 8 is a cross-sectional side view of a device assembly that may include one or more microelectronic assemblies in accordance with any of the embodiments disclosed herein. FIG. 9 is a block diagram of an example computing device that may include one or more microelectronic assemblies in accordance with any of the embodiments disclosed herein. DETAILED DESCRIPTION The structures and assemblies disclosed herein may include a glass core, also referred to herein as a “glass layer,” with TGVs extending through the glass core for front-to-back connections between two different substrates. A substrate may include a dielectric material with conductive pathways therein that are typically formed on a surface of the glass core. The conductive pathways through the dielectric material may provide routing for design flexibility, and the uniform diameters of the TGVs may