US-20260130246-A1 - PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME

Abstract

A package substrate a core having a first surface and a second surface that is opposite to the first surface in a vertical direction, the first surface and the second surface being substantially flat, the core including glass and a first recess in the first surface, a first bonding layer contacting the first surface of the core and filling the first recess, a through electrode extending from the first surface through the core in the vertical direction, the through electrode being spaced apart from the first recess in a horizontal direction, a first wiring structure on the first bonding layer and contacting the through electrode, a first insulation layer structure on the first bonding layer and partially covering the first wiring structure; and a first protective layer on the first insulation layer structure and covering an upper surface of a portion of the first wiring structure.

Inventors

• Okgyeong PARK

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260507

Application Date

20251017

Priority Date

20241107

Claims (20)

1. 1 . A package substrate comprising: a core having a first surface and a second surface that is opposite to the first surface in a vertical direction, the first surface and the second surface being substantially flat, the core including glass and a first recess in the first surface; a first bonding layer contacting the first surface of the core and filling the first recess; a through electrode extending from the first surface through the core in the vertical direction, the through electrode being spaced apart from the first recess in a horizontal direction; a first wiring structure on the first bonding layer and contacting the through electrode; a first insulation layer structure on the first bonding layer and at least partially covering the first wiring structure; and a first protective layer on the first insulation layer structure and covering an upper surface of a portion of the first wiring structure.
2. 2 . The package substrate according to claim 1 , wherein a width in the horizontal direction of the first recess is substantially constant in the vertical direction.
3. 3 . The package substrate according to claim 1 , wherein a width in the horizontal direction of the first recess gradually decreases as a distance from the first surface of the core increases in the vertical direction.
4. 4 . The package substrate according to claim 1 , wherein a width in the horizontal direction of the first recess gradually decreases and increases again as a distance from the first surface of the core increases in the vertical direction.
5. 5 . The package substrate according to claim 1 , wherein a cross-section in the vertical direction of the first recess has a staircase shape.
6. 6 . The package substrate according to claim 1 , further comprising a plurality of first recesses that are spaced apart from each other in the horizontal direction, the first recess being one of the plurality of first recesses.
7. 7 . The package substrate according to claim 1 , wherein the first bonding layer includes epoxy, and the first insulation layer structure includes Ajinomoto build-up film.
8. 8 . The package substrate according to claim 1 , wherein the core further includes a second recess in the second surface of the core.
9. 9 . The package substrate according to claim 8 , wherein the through electrode extends from the first surface, through the core, to the second surface in the vertical direction, and wherein the package substrate further comprises: a second bonding layer contacting the second surface of the core and filling the second recess; a second wiring structure on the second bonding layer and contacting the through electrode; a second insulation layer structure on the second bonding layer and at least partially covering the second wiring structure; and a second protective layer on the second insulation layer structure and covering a lower surface of a portion of the second wiring structure.
10. 10 . The package substrate according to claim 9 , wherein the first recess and the second recess are arranged symmetrically with respect to a line passing through the core in the horizontal direction.
11. 11 . A package substrate comprising: a core including glass, the core having a first surface and a second surface opposite the first surface in a vertical direction and a first recess in the first surface; a first bonding layer in the first recess, the first bonding layer including a first organic insulating material; a second bonding layer contacting the first surface of the core and an upper surface of the first bonding layer, the second bonding layer including a second organic insulating material that is different from the first organic insulating material; a through electrode extending from the first surface through the core in the vertical direction, the through electrode being spaced apart from the first recess in a horizontal direction; a first wiring structure on the first bonding layer and contacting the through electrode; a first insulation layer structure on the first bonding layer and at least partially covering the first wiring structure; and a first protective layer on the first insulation layer structure and covering an upper surface of a portion of the first wiring structure.
12. 12 . The package substrate according to claim 11 , wherein a width in the horizontal direction of the first recess gradually decreases as a distance from the first surface of the core increases in the vertical direction.
13. 13 . The package substrate according to claim 11 , wherein a width in the horizontal direction of the first recess gradually decreases and increases again as a distance from the first surface of the core increases in the vertical direction.
14. 14 . The package substrate according to claim 11 , wherein a cross-section in the vertical direction of the first recess has a staircase shape.
15. 15 . The package substrate according to claim 11 , further comprising a plurality of first recesses that are spaced apart from each other in the horizontal direction, the first recess being one of the plurality of first recesses.
16. 16 . The package substrate according to claim 11 , wherein the through hole extends from the first surface, through the core, to the second surface in the vertical direction, wherein the core further includes a second recess in the second surface of the core, and wherein the package substrate further comprises: a third bonding layer contacting the second surface of the core and filling the second recess; a second wiring structure on the third bonding layer and contacting the through electrode; a second insulation layer structure on the third bonding layer and at least partially covering the second wiring structure; and a second protective layer on the second insulation layer structure and covering a lower surface of a portion of the second wiring structure.
17. 17 . A semiconductor package comprising: a package substrate including: a core including glass and having a first surface and a second surface that is opposite to the first surface in a vertical direction, the first surface and the second surface being substantially flat and the core including a first recess in the first surface; a first bonding layer contacting the first surface of the core and filling the first recess; a through electrode extending from the first surface through the core in the vertical direction, the through electrode being spaced apart from the first recess in a horizontal direction; a first wiring structure on the first bonding layer and contacting the through electrode; a first insulation layer structure on the first bonding layer and at least partially covering the first wiring structure; and a first protective layer on the first insulation layer structure and covering an upper surface of a first portion of the first wiring structure; a semiconductor chip on the package substrate, the semiconductor chip including a conductive pad; a first conductive connection member contacting the conductive pad of the semiconductor chip, the conductive connection member being electrically connected to a second portion of the first wiring structure; and a molding member on the package substrate and covering the semiconductor chip and a sidewall of the first conductive connection member.
18. 18 . The semiconductor package according to claim 17 , wherein the through hole extends from the first surface, through the core, to the second surface in the vertical direction, wherein the core of the package substrate further includes a second recess in the second surface of the core, wherein the package substrate further includes: a second bonding layer contacting the second surface of the core and filling the second recess; a second wiring structure on the second bonding layer and contacting the through electrode; a second insulation layer structure on the second bonding layer and at least partially covering the second wiring structure; and a second protective layer on the second insulation layer structure and covering a lower surface of a first portion of the second wiring structure, and wherein the semiconductor package further comprises a second conductive connection member contacting a lower surface of a second portion of the second wiring structure.
19. 19 . The semiconductor package according to claim 17 , wherein the first recess does not overlap the semiconductor chip in the vertical direction.
20. 20 . The package substrate according to claim 17 , further comprising: an interposer between the package substrate and the first conductive connection member, the interposer being electrically connected to the first wiring structure and the first conductive connection member; a heat dissipation member contacting an upper surface of the semiconductor chip; and a heat slug contacting the heat dissipation member.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is based on and claims priority under 35 U.S. C. § 119 to Korean Patent Application No. 10-2024-0156874, filed on Nov. 7, 2024 in the Korean Intellectual Property Office (KIPO), the contents of which being herein incorporated by reference in their entirety. BACKGROUND Example embodiments relate to a package substrate and a semiconductor package including the same. As an area of a package substrate increases, warpage occurs in the package substrate, and a method of increasing the stiffness of the core is needed. SUMMARY It is an aspect to provide a package substrate having enhanced electrical characteristics. It is another aspect to provide a semiconductor package having enhanced electrical characteristics. According to an aspect of one or more example embodiments, there is provided a package substrate comprising a core having a first surface and a second surface that is opposite to the first surface in a vertical direction, the first surface and the second surface being substantially flat, the core including glass and a first recess in the first surface; a first bonding layer contacting the first surface of the core and filling the first recess; a through electrode extending from the first surface through the core in the vertical direction, the through electrode being spaced apart from the first recess in a horizontal direction; a first wiring structure on the first bonding layer and contacting the through electrode; a first insulation layer structure on the first bonding layer and at least partially covering the first wiring structure; and a first protective layer on the first insulation layer structure and covering an upper surface of a portion of the first wiring structure. According another aspect of one or more example embodiments, there is provided a package substrate comprising a core including glass, the core having a first surface and a second surface opposite the first surface in a vertical direction and a first recess in the first surface; a first bonding layer in the first recess, the first bonding layer including a first organic insulating material; a second bonding layer contacting the first surface of the core and an upper surface of the first bonding layer, the second bonding layer including a second organic insulating material that is different from the first organic insulating material; a through electrode extending from the first surface through the core in the vertical direction, the through electrode being spaced apart from the first recess in a horizontal direction; a first wiring structure on the first bonding layer and contacting the through electrode; a first insulation layer structure on the first bonding layer and at least partially covering the first wiring structure; and a first protective layer on the first insulation layer structure and covering an upper surface of a portion of the first wiring structure. According to yet another aspect of one or more example embodiments, there is provided a semiconductor package comprising a package substrate including a core including glass and having a first surface and a second surface that is opposite to the first surface in a vertical direction, the first surface and the second surface being substantially flat and the core including a first recess in the first surface; a first bonding layer contacting the first surface of the core and filling the first recess; a through electrode extending from the first surface through the core in the vertical direction, the through electrode being spaced apart from the first recess in a horizontal direction; a first wiring structure on the first bonding layer and contacting the through electrode; a first insulation layer structure on the first bonding layer and at least partially covering the first wiring structure; and a first protective layer on the first insulation layer structure and covering an upper surface of a first portion of the first wiring structure; a semiconductor chip on the package substrate, the semiconductor chip including a conductive pad; a first conductive connection member contacting the conductive pad of the semiconductor chip, the conductive connection member being electrically connected to a second portion of the first wiring structure; and a molding member on the package substrate and covering the semiconductor chip and a sidewall of the first conductive connection member. BRIEF DESCRIPTION OF THE DRAWINGS The above and other aspects will be more clear based on the following description in combination with the drawings, in which: FIG. 1 is a cross-sectional view illustrating a package substrate in accordance with example embodiments; FIGS. 2 to 6 are cross-sectional views illustrating a method of manufacturing a package substrate in accordance with example embodiments; FIG. 7 is a cross-sectional view illustrating a package substrate in accordance with example embodiments; FIGS. 8 to 10 are cross-sectional views illustrat