US-20260130247-A1 - SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME

Abstract

A semiconductor package fabrication method includes attaching a first surface of a via structure having an opening to a surface of an adhesive member, forming conductive connectors and a bridge chip on the surface of the adhesive member and in the opening, removing the adhesive member, forming a first redistribution substrate on the first surface of the via structure, mounting chip structures on the first redistribution substrate, and forming a second redistribution substrate on a second surface of the via structure. The bridge chip has a first surface and an opposite second surface. The first surface of the bridge chip and the first surface of the via structure may be located at respective different levels.

Inventors

• Daeyeun CHOI
• Tae-Ho KO
• Un-Byoung Kang
• Seokbong Park

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260507

Application Date

20250507

Priority Date

20241101

Claims (20)

1. 1 . A method of fabricating a semiconductor package, the method comprising: attaching a first surface of a via structure to a surface of an adhesive member, the via structure comprising an opening; forming a plurality of conductive connectors and a bridge chip on the surface of the adhesive member and in the opening of the via structure; removing the adhesive member; forming a first redistribution substrate on the first surface of the via structure; mounting a plurality of chip structures on the first redistribution substrate; and forming a second redistribution substrate on an opposite second surface of the via structure, wherein the bridge chip has a first surface and an opposite second surface, and wherein the first surface of the bridge chip and the first surface of the via structure are located at respective different levels.
2. 2 . The method of claim 1 , wherein the via structure comprises: a via base layer; and a plurality of conductive posts extending through the via base layer.
3. 3 . The method of claim 2 , wherein the via base layer comprises at least one selected from silicon, glass, or organics.
4. 4 . The method of claim 2 , wherein the organics comprise at least one selected from fiber glass epoxy, glass paper epoxy, Teflon™, resin coated copper (RCC), or ceramics.
5. 5 . The method of claim 2 , wherein a variation in heights of the plurality of conductive posts is less than about 10 μm.
6. 6 . The method of claim 5 , wherein the heights of the plurality of conductive posts are about 100 to 250 μm.
7. 7 . The method of claim 2 , wherein the plurality of conductive posts are spaced apart from each other in a first direction and a second direction that are parallel to the first surface of the via structure, wherein the first direction and the second direction are transverse to each other, wherein a first distance in the first direction between conductive posts that neighbor each other in the first direction is about 0.8 to 1.2 times a diameter of the conductive posts.
8. 8 . The method of claim 7 , wherein a second distance in the second direction between conductive posts that neighbor each other in the second direction is about 0.8 to 1.2 times the diameter of the conductive posts.
9. 9 . The method of claim 1 , further comprising, after the forming the plurality of conductive connectors and the bridge chip, forming a bridge mold layer on the surface of the adhesive member and in the opening of the via structure, the bridge mold layer covering the plurality of conductive connectors and the bridge chip.
10. 10 . The method of claim 1 , further comprising, after the forming the plurality of conductive connectors and the bridge chip, and before the removing the adhesive member, forming a first carrier substrate on the second surface of the via structure.
11. 11 . The method of claim 1 , wherein the plurality of chip structures comprise a base chip and a unit chip package that are spaced apart from each other in a direction parallel to the first surface of the via structure.
12. 12 . The method of claim 1 , further comprising, after mounting the plurality of chip structures on the first redistribution substrate, forming on the first redistribution substrate a mold layer that covers the plurality of chip structures.
13. 13 . A method of fabricating a semiconductor package, the method comprising: attaching a first surface of a via structure to a surface of an adhesive member, the via structure comprising an opening; forming a plurality of conductive connectors and a bridge chip on the surface of the adhesive member and in the opening of the via structure; forming a first carrier substrate on an opposite second surface of the via structure; removing the adhesive member; forming a first redistribution substrate on the first surface of the via structure; mounting a plurality of chip structures on the first redistribution substrate; forming on the first redistribution substrate a mold layer that covers the plurality of chip structures; removing the first carrier substrate; forming a second carrier substrate on the mold layer; and forming a second redistribution substrate on the second surface of the via structure, wherein the bridge chip has a first surface and an opposite second surface, and wherein the first surface of the bridge chip and the first surface of the via structure are located at respective different levels.
14. 14 . The method of claim 13 , wherein the via structure comprises: a via base layer; and a plurality of conductive posts extending within the via base layer, wherein the plurality of conductive posts are spaced apart from each other in a first direction and a second direction that are parallel to the first surface of the via structure, wherein the first direction and the second direction are transverse to each other.
15. 15 . The method of claim 14 , wherein a variation in heights of the plurality of conductive posts is less than about 10 μm.
16. 16 . The method of claim 14 , wherein the plurality of conductive posts have a cylindrical shape with a diameter of about 40 to 100 μm.
17. 17 . The method of claim 13 , wherein the plurality of chip structures comprise a base chip and a unit chip package that are spaced apart from each other in a direction parallel to the first surface of the via structure.
18. 18 . The method of claim 13 , further comprising a bridge mold layer on the surface of the adhesive member and in the opening of the via structure, the bridge mold layer covering the plurality of conductive connectors and the bridge chip.
19. 19 . The method of claim 13 , further comprising, after the forming the second redistribution substrate, removing the second carrier substrate; forming a photoresist film on the second redistribution substrate; and planarizing the mold layer to expose surfaces of the plurality of chip structures.
20. 20 . A method of manufacturing a semiconductor package, the method comprising: attaching a first surface of a via structure to a surface of an adhesive member, wherein the via structure comprises a base layer, a plurality of conductive posts extending through the base layer, and an opening; forming a plurality of conductive connectors and a bridge chip on the surface of the adhesive member and in the opening of the via structure; forming a bridge mold layer on the surface of the adhesive member and in the opening of the via structure, the bridge mold layer covering the plurality of conductive connectors and the bridge chip; removing the adhesive member; forming a first redistribution substrate on the first surface of the via structure; mounting a plurality of chip structures on the first redistribution substrate; and forming a second redistribution substrate on an opposite second surface of the via structure.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims priority under 35 U.S.C § 119 to Korean Patent Application No. 10-2024-0153610 filed on Nov. 1, 2024 in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference in its entirety. BACKGROUND The present inventive concepts relate to a semiconductor package, and more particularly, to a semiconductor package including a redistribution substrate and a method of fabricating the same. With the development of the electronic industry, electronic products have increasing demands for high performance, high speed, and compact size. To meet the trend, there has recently been developed a packaging technology in which a plurality of semiconductor chips are mounted in a single package. A semiconductor package is provided to implement an integrated circuit chip to qualify for use in electronic products. Typically, in the semiconductor package, a semiconductor chip is mounted on a printed circuit board (PCB) and bonding wires or bumps are used to electrically connect the semiconductor chip to the printed circuit board. With the recent development of the electronic industry, the semiconductor package is variously developed to reach the goal of compact size, small weight, and/or low manufacturing cost. In addition, many kinds of semiconductor packages show up with the expansion of their application field such as high-capacity mass storage devices. SUMMARY Some embodiments of the present inventive concepts provide a semiconductor package with improved reliability and electrical properties and a method of fabricating the same. An object of the present inventive concepts is not limited to the mentioned above, and other objects which have not been mentioned above will be clearly understood to those skilled in the art from the following description. According to some embodiments of the present inventive concepts, a method of fabricating a semiconductor package may include attaching a first surface of a via structure to a surface of an adhesive member, the via structure having an opening; forming a plurality of conductive connectors and a bridge chip on the surface of the adhesive member and in the opening of the via structure; removing the adhesive member; forming a first redistribution substrate on the first surface of the via structure; mounting a plurality of chip structures on the first redistribution substrate; and forming a second redistribution substrate on an opposite second surface of the via structure. The bridge chip may have a first surface and an opposite second surface. The first surface of the bridge chip and the first surface of the via structure may be located at respective different levels. According to some embodiments of the present inventive concepts, a method of fabricating a semiconductor package may include attaching a first surface of a via structure to a surface of an adhesive member, the via structure having an opening; forming a plurality of conductive connectors and a bridge chip on the surface of the adhesive member and in the opening of the via structure; forming a first carrier substrate on an opposite second surface of the via structure; removing the adhesive member; forming a first redistribution substrate on the first surface of the via structure; mounting a plurality of chip structures on the first redistribution substrate; forming on the first redistribution substrate a mold layer that covers the plurality of chip structures; removing the first carrier substrate; forming a second carrier substrate on the mold layer; and forming a second redistribution substrate on the second surface of the via structure. The bridge chip may have a first surface and an opposite second surface. The first surface of the bridge chip and the first surface of the via structure may be located at respective different levels. According to some embodiments of the present inventive concepts, a method of manufacturing a semiconductor package includes attaching a first surface of a via structure to a surface of an adhesive member, wherein the via structure comprises a base layer, a plurality of conductive posts extending through the base layer, and an opening; forming a plurality of conductive connectors and a bridge chip on the surface of the adhesive member and in the opening of the via structure; forming a bridge mold layer on the surface of the adhesive member and in the opening of the via structure, the bridge mold layer covering the plurality of conductive connectors and the bridge chip; removing the adhesive member; forming a first redistribution substrate on the first surface of the via structure; mounting a plurality of chip structures on the first redistribution substrate; and forming a second redistribution substrate on an opposite second surface of the via structure. BRIEF DESCRIPTION OF DRAWINGS FIG. 1 illustrates a plan view showing a semiconductor package according to some embodiments of the present invent