US-20260130249-A1 - SEMICONDUCTOR MODULE WITH POWER BRIDGE FOR INTEGRATED DIE INTERCONNECTION

Abstract

A semiconductor module may include a first substrate having a first substrate surface that includes an area, a first semiconductor die disposed within the area on the first substrate surface, and a second semiconductor die disposed within the area on the first substrate surface. The semiconductor module may further include a second substrate that has a second substrate surface that spans the area and faces the first semiconductor die, the second semiconductor die, and the area, with the second substrate surface having a dielectric layer formed thereon with a metallization layer formed on the dielectric layer that includes patterned metals configured to electrically connect the first semiconductor die and the second semiconductor die to each other and to at least one conductive element on the first substrate surface that is outside of the area.

Inventors

• Christopher Lee Tessler
• Michael J. Seddon
• Dinesh Ramanathan
• Anders Soren Lind
• Vijay B. Rentala

Assignees

• SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Dates

Publication Date

20260507

Application Date

20251031

Claims (20)

1. 1 . A semiconductor module, comprising: a first substrate having a first substrate surface that includes an area; a first semiconductor die disposed within the area on the first substrate surface; a second semiconductor die disposed within the area on the first substrate surface; and a second substrate that has a second substrate surface that spans the area and faces the first semiconductor die, the second semiconductor die, and the area, the second substrate surface having a dielectric layer formed thereon with a metallization layer formed on the dielectric layer that includes patterned metals configured to electrically connect the first semiconductor die and the second semiconductor die to each other and to at least one conductive element on the first substrate surface that is outside of the area.
2. 2 . The semiconductor module of claim 1 , wherein the second substrate comprises at least one of Silicon or Gallium Nitride.
3. 3 . The semiconductor module of claim 1 , wherein the first semiconductor die has a first height and the second semiconductor die has a second height that is different from the first height, and further comprising: a height adjustment structure between the second substrate and both of the first semiconductor die and the second semiconductor die that maintains opposed outer surfaces of the semiconductor module in parallel with one another.
4. 4 . The semiconductor module of claim 3 , wherein the height adjustment structure includes a first cavity and a second cavity formed in the second substrate and having a first depth and a second depth, respectively, and further wherein the first semiconductor die is disposed within the first cavity and the second semiconductor die is disposed within the second cavity.
5. 5 . The semiconductor module of claim 4 , wherein the first cavity and the second cavity have sloped walls and with the dielectric layer and the metallization layer formed thereon.
6. 6 . The semiconductor module of claim 3 , wherein the height adjustment structure includes at least one conductive layer disposed between at least one of the first semiconductor die and the second semiconductor die, and having a thickness that maintains the opposed outer surfaces of the semiconductor module in parallel with one another.
7. 7 . The semiconductor module of claim 1 , wherein the second substrate has an outer surface opposed to the second substrate surface, and further comprising a device formed on the outer surface.
8. 8 . The semiconductor module of claim 1 , wherein the second substrate has an outer surface opposed to the second substrate surface, and further comprising a heatsink formed on the outer surface.
9. 9 . The semiconductor module of claim 1 , wherein the second substrate is directly connected to the first substrate.
10. 10 . The semiconductor module of claim 1 , further comprising a sensor disposed on the second substrate.
11. 11 . A semiconductor module, comprising: a first substrate having a first substrate surface that includes an area; a first semiconductor die disposed within the area on the first substrate surface and having a first height; a second semiconductor die disposed within the area on the first substrate surface and having a second height; a second substrate that has a second substrate surface that spans the area and faces the first semiconductor die, the second semiconductor die, and the area, the second substrate surface having a dielectric layer formed thereon with a metallization layer formed on the dielectric layer that includes patterned metals configured to electrically connect the first semiconductor die and the second semiconductor die to each other; and a height adjustment structure between the second substrate and both of the first semiconductor die and the second semiconductor die that maintains opposed outer surfaces of the semiconductor module in parallel with one another.
12. 12 . The semiconductor module of claim 11 , wherein the second substrate is directly connected to the first substrate and the patterned metals are configured to electrically connect at least one of the first semiconductor die and the second semiconductor die to at least one conductive element on the first substrate surface that is outside of the area.
13. 13 . The semiconductor module of claim 12 , wherein the height adjustment structure includes a first cavity and a second cavity formed in the second substrate and having a first depth and a second depth, respectively, and further wherein the first semiconductor die is disposed within the first cavity and the second semiconductor die is disposed within the second cavity.
14. 14 . The semiconductor module of claim 13 , wherein the first cavity and the second cavity have sloped walls and with the dielectric layer and the metallization layer formed thereon.
15. 15 . The semiconductor module of claim 11 , wherein the height adjustment structure includes at least one conductive layer disposed between at least one of the first semiconductor die and the second semiconductor die, and having a thickness that maintains the opposed outer surfaces of the semiconductor module in parallel with one another.
16. 16 . The semiconductor module of claim 11 , wherein the second substrate comprises at least one of Silicon or Gallium Nitride.
17. 17 . A method of making a semiconductor module, comprising: disposing, on a first substrate having a first substrate surface that includes an area, a first semiconductor die and a second semiconductor die disposed within the area on the first substrate surface; forming a second substrate with a second substrate surface having a dielectric layer formed thereon with a metallization layer formed on the dielectric layer that includes patterned metals; and connecting the second substrate to the first substrate, with the second substrate surface of the second substrate spanning the area and facing the first semiconductor die and a second semiconductor die within the area, and with the patterned metals configured to electrically connect the first semiconductor die and the second semiconductor die to each other and to at least one conductive element on the first substrate surface that is outside of the area.
18. 18 . The method of claim 17 , further comprising: providing a height adjustment structure between the second substrate and both of the first semiconductor die and the second semiconductor die that maintains opposed outer surfaces of the semiconductor module in parallel with one another.
19. 19 . The method of claim 18 , further comprising providing the height adjustment structure including: forming a first cavity and a second cavity in the second substrate with a first depth and a second depth, respectively; disposing the first semiconductor die within the first cavity; and disposing the second semiconductor die within the second cavity.
20. 20 . The method of claim 18 , further comprising providing the height adjustment structure including: providing at least one conductive layer disposed between at least one of the first semiconductor die and the second semiconductor die, with a thickness that maintains the opposed outer surfaces of the semiconductor module in parallel with one another.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims the benefit of and priority to (1) U.S. Provisional Application No. 63/715,912, filed Nov. 4, 2024, and (2) U.S. Provisional Application No. 63/736,415, filed Dec. 19, 2024, and to U.S. Non-provisional application xx/xxx,xxx, filed concurrently herewith and titled SEMICONDUCTOR PACKAGING WITH EMBEDDED DEVICE AND REDISTRIBUTION LAYER, which are incorporated by reference herein in their entireties. TECHNICAL FIELD This description relates to power semiconductor devices. BACKGROUND Conventional power semiconductor modules may utilize wire bonds to establish interconnects between a die and the package and/or between individual dies. However, wire bonds are associated with a number of shortcomings, including, e.g., elevated inductance and resistivity, which may impair switching performance. Moreover, wire bonds tend to consume undesirable quantities of space, may be unreliable, and, once connected, are difficult to revise or rework. Another widely adopted technique involves die embedding within power semiconductor packages. Such approaches provide electrical access to both the top and bottom of the power die, which may enhance connectivity. Such methods, while effective for two-sided access, also introduce process complexities, as well as difficulties in ensuring uniform electrical properties across multiple parallel dies, and may therefore struggle with providing synchronized switching, e.g., in half-bridge configurations. The inability to test and tune resistance and inductance prior to assembly limits the optimization of such modules under demanding conditions. Traditional packaging for power devices often fails to provide desired levels of reliability, as well. For example, differences in thermal expansion characteristics between a die and a package (e.g., ceramic) may result in cracking or other failures. Further, known techniques struggle to meet demand with respect to manufacturing compact devices that also provide desired thermal management. For example, heatsinks that provide sufficient heat dispersal are often too large to provide a final package of desired size. Further, mold materials or organic materials used in embedded packages tend to be poor heat conductors. The above difficulties, and others, are exacerbated by the need to produce power devices at scale. As a result, current power devices and associated packaging techniques are unable to meet market demand. SUMMARY According to one general aspect a semiconductor module, comprises a first substrate having a first substrate surface that includes an area, a first semiconductor die disposed within the area on the first substrate surface, a second semiconductor die disposed within the area on the first substrate surface, and a second substrate that has a second substrate surface that spans the area and faces the first semiconductor die, the second semiconductor die, and the area, the second substrate surface having a dielectric layer formed thereon with a metallization layer formed on the dielectric layer that includes patterned metals configured to electrically connect the first semiconductor die and the second semiconductor die to each other and to at least one conductive element on the first substrate surface that is outside of the area. According to another general aspect, a semiconductor module, comprises a first substrate having a first substrate surface that includes an area, a first semiconductor die disposed within the area on the first substrate surface and having a first height, a second semiconductor die disposed within the area on the first substrate surface and having a second height, a second substrate that has a second substrate surface that spans the area and faces the first semiconductor die, the second semiconductor die, and the area, the second substrate surface having a dielectric layer formed thereon with a metallization layer formed on the dielectric layer that includes patterned metals configured to electrically connect the first semiconductor die and the second semiconductor die to each other, and a height adjustment structure between the second substrate and both of the first semiconductor die and the second semiconductor die that maintains opposed outer surfaces of the semiconductor module in parallel with one another. According to another general aspect, a method of making a semiconductor module, comprises disposing, on a first substrate having a first substrate surface that includes an area, a first semiconductor die and a second semiconductor die disposed within the area on the first substrate surface, forming a second substrate with a second substrate surface having a dielectric layer formed thereon with a metallization layer formed on the dielectric layer that includes patterned metals, and connecting the second substrate to the first substrate, with the second substrate surface of the second substrate spanning the area and facing the first semiconductor d