US-20260130251-A1 - POWER SEMICONDUCTOR PACKAGES AND RELATED METHODS

Abstract

Implementations of a substrate may include a semiconductor material; a redistribution layer coupled to a first largest planar surface of the semiconductor material; and a hollow via extending from a second largest planar surface of the semiconductor material completely through a thickness of the semiconductor material, the hollow via directly coupled with the redistribution layer.

Inventors

• Christopher Lee Tessler

Assignees

• SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Dates

Publication Date

20260507

Application Date

20241104

Claims (20)

1. 1 . A substrate comprising: a semiconductor material; a redistribution layer coupled to a first largest planar surface of the semiconductor material; and a hollow via extending from a second largest planar surface of the semiconductor material completely through a thickness of the semiconductor material, the hollow via directly coupled with the redistribution layer.
2. 2 . The substrate of claim 1 , wherein the redistribution layer comprises at least one thick copper layer.
3. 3 . The substrate of claim 1 , wherein the redistribution layer comprises at least one dielectric layer and at least one layer of one of a solderable metal or a sinterable metal.
4. 4 . The substrate of claim 1 , wherein the semiconductor material is thinned from an initial thickness.
5. 5 . The substrate of claim 1 , wherein the semiconductor material is silicon carbide.
6. 6 . The substrate of claim 1 , wherein the semiconductor material is silicon.
7. 7 . The substrate of claim 6 , further comprising an oxide layer between the redistribution layer and the semiconductor material.
8. 8 . The substrate of claim 6 , further comprising an oxide layer on the second largest planar surface of the semiconductor material.
9. 9 . The substrate of claim 1 , further comprising a backmetal layer coupled to the second largest planar surface of the semiconductor material.
10. 10 . A method of embedding a semiconductor die, the method comprising: providing a silicon substrate comprising a first oxide layer thereon; forming at least one opening in the first oxide layer; etching a cavity into the silicon substrate at the at least one opening in the first oxide layer; forming a second oxide layer in the cavity; forming a thick copper layer on the first oxide layer and on the second oxide layer; patterning the thick copper layer; sintering at least one semiconductor die to the thick copper layer in the cavity; filling a gap between the at least one semiconductor die and the thick copper layer in the cavity with a polyimide; forming a layer of photosensitive polymer over the at least one semiconductor die, the thick copper layer, and the first oxide layer; patterning the layer of photosensitive polymer to form a plurality of openings therein; forming a first copper layer in the plurality of openings; and forming a second copper layer over the layer of photosensitive polymer and the first copper layer.
11. 11 . The method of claim 10 , wherein forming the first copper layer and forming the second copper layer occur simultaneously.
12. 12 . The method of claim 10 , further comprising forming a seed layer on the second oxide layer before forming the thick copper layer.
13. 13 . The method of claim 10 , further comprising baking the polyimide.
14. 14 . The method of claim 10 , further comprising coupling one of a redistribution layer or another semiconductor die to the second copper layer.
15. 15 . A method of embedding a semiconductor die, the method comprising: providing a silicon substrate comprising an oxide layer thereon; forming a thick copper layer on the oxide layer; patterning the thick copper layer; applying a first photosensitive polyimide over the thick copper layer; patterning the first photosensitive polyimide to form an opening therein; one of sintering or soldering a semiconductor die in the opening; forming a first copper layer on the first photosensitive polyimide and the semiconductor die; applying a second photosensitive polyimide over the first copper layer; patterning the second photosensitive polyimide; forming a second copper layer on the second photosensitive polyimide; and coupling one of a redistribution layer or another semiconductor die onto the second copper layer.
16. 16 . The method of claim 15 , further comprising forming a seed layer on the oxide layer before forming the thick copper layer.
17. 17 . The method of claim 15 , further comprising filling a space around the semiconductor die with a polyimide before forming the first copper layer.
18. 18 . The method of claim 15 , wherein forming the first copper layer further comprises forming vias and traces at the same time.
19. 19 . The method of claim 15 , wherein forming the first copper layer further comprises first forming vias and then forming traces.
20. 20 . The method of claim 15 , wherein forming the second copper layer further comprises one of: forming vias and traces at the same time; or first forming vias and then forming traces.

Description

BACKGROUND 1. Technical Field Aspects of this document relate generally to semiconductor package. More specific implementations involve power semiconductor packages. 2. Background Semiconductor packages have been devised that work to provide mechanical support and protection for one or more semiconductor die included in the packages. Other semiconductor packages work to prevent damage to the semiconductor die from electrostatic discharge. Still other semiconductor packages work to assist with preventing damage to a semiconductor die included in the package from shock, vibration, or humidity. SUMMARY Implementations of a substrate may include a semiconductor material; a redistribution layer coupled to a first largest planar surface of the semiconductor material; and a hollow via extending from a second largest planar surface of the semiconductor material completely through a thickness of the semiconductor material, the hollow via directly coupled with the redistribution layer. Implementations of a substrate may include one, all, or any of the following: The redistribution layer may include at least one thick copper layer. The redistribution layer may include at least one dielectric layer and at least one layer of one of a solderable metal or a sinterable metal. The semiconductor material may be thinned from an initial thickness. The semiconductor material may be silicon carbide. The semiconductor material may be silicon. The substrate may include an oxide layer between the redistribution layer and the semiconductor material. The substrate may include an oxide layer on the second largest planar surface of the semiconductor material. The substrate may include a backmetal layer coupled to the second largest planar surface of the semiconductor material. Implementations of a method of embedding a semiconductor die may include providing a silicon substrate including a first oxide layer thereon; forming at least one opening in the first oxide layer; etching a cavity into the silicon substrate at the at least one opening in the first oxide layer; forming a second oxide layer in the cavity; forming a thick copper layer on the first oxide layer and on the second oxide layer; and patterning the thick copper layer. The method may include sintering at least one semiconductor die to the thick copper layer in the cavity; filling a gap between the at least one semiconductor die and the thick copper layer in the cavity with a polyimide; forming a layer of photosensitive polymer over the at least one semiconductor die, the thick copper layer, and the first oxide layer; and patterning the layer of photosensitive polymer to form a plurality of openings therein. The method may include forming a first copper layer in the plurality of openings; and forming a second copper layer over the layer of photosensitive polymer and the first copper layer. Implementations of a method of embedding a semiconductor die may include one, all, or any of the following: Forming the first copper layer and forming the second copper layer may occur simultaneously. The method may include forming a seed layer on the second oxide layer before forming the thick copper layer. The method may include baking the polyimide. The method may include coupling one of a redistribution layer or another semiconductor die to the second copper layer. Implementations of a method of embedding a semiconductor die may include providing a silicon substrate including an oxide layer thereon; forming a thick copper layer on the oxide layer; patterning the thick copper layer; applying a first photosensitive polyimide over the thick copper layer; and patterning the first photosensitive polyimide to form an opening therein. The method may include one of sintering or soldering a semiconductor die in the opening; forming a first copper layer on the first photosensitive polyimide and the semiconductor die; and applying a second photosensitive polyimide over the first copper layer. The method may include patterning the second photosensitive polyimide; forming a second copper layer on the second photosensitive polyimide; and coupling one of a redistribution layer or another semiconductor die onto the second copper layer. Implementations of a method of embedding a semiconductor die may include one, all, or any of the following: The method may include forming a seed layer on the oxide layer before forming the thick copper layer. The method may include filling a space around the semiconductor die with a polyimide before forming the first copper layer. Forming the first copper layer further may include forming vias and traces at the same time. Forming the first copper layer further may include first forming vias and then forming traces. Forming the second copper layer further may include one of: forming vias and traces at the same time; or first forming vias and then forming traces. The foregoing and other aspects, features, and advantages will be apparent to those artisans of ordinary skil