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US-20260130255-A1 - CHIP PACKAGING METHOD AND CHIP PACKAGING STRUCTURE

US20260130255A1US 20260130255 A1US20260130255 A1US 20260130255A1US-20260130255-A1

Abstract

Provided are a chip packaging method and a chip packaging structure. The method includes: arranging a spacer on at least one of a first surface of a package substrate and a second surface of a chip; arranging a first adhesive on at least one of the first surface, the second surface, or the spacer; bringing together the package substrate and the chip, to sandwich the spacer between the first surface and the second surface, and adhere the first surface to the second surface by the first adhesive; and curing the first adhesive. With the chip packaging structure generated based on the above-mentioned method, a shear displacement of the first adhesive can be increased under a given load to reduce an attachment area of the chip, ensuring a height of the first adhesive.

Inventors

  • Sae Won Lee
  • Qin Zhou

Assignees

  • inSync Resonance Inc

Dates

Publication Date
20260507
Application Date
20241106

Claims (17)

  1. 1 . A chip packaging method, comprising: a step S 1 of arranging a spacer on at least one of a first surface of a package substrate and a second surface of a chip; a step S 2 of arranging a first adhesive on at least one of the first surface, the second surface, or the spacer; a step S 3 of bringing together the first surface of the package substrate and the second surface of the chip, to sandwich the spacer between the first surface and the second surface; and to adhere the first surface to the second surface by the first adhesive, or adhere the first surface to the second surface by the spacer and the first adhesive, wherein a distribution area of the first adhesive at the second surface is smaller than an area of the second surface; and a step S 4 of curing the first adhesive.
  2. 2 . The chip packaging method according to claim 1 , wherein the step S 1 comprises: a step S 11 of arranging a second adhesive on at least one of the first surface of the package substrate and the second surface of the chip; and a step S 12 of curing the second adhesive, the spacer being formed by the cured second adhesive.
  3. 3 . The chip packaging method according to claim 2 , wherein the second adhesive is made of a same material as the first adhesive.
  4. 4 . The chip packaging method according to claim 2 , wherein in the step S 11 of arranging the second adhesive, a plurality of second adhesives in equal amounts are arranged at a plurality of positions on at least one of the first surface and the second surface, the plurality of positions being separated from each other.
  5. 5 . The chip packaging method according to claim 4 , wherein in the step S 12 of curing the second adhesive, the first surface or the second surface on which the plurality of second adhesives are arranged is kept horizontally stationary, allowing a plurality of spacers formed by curing the plurality of second adhesives at the plurality of positions on the at least one of the first surface and the second surface to be of equal height and having each a smooth arc top surface.
  6. 6 . The chip packaging method according to claim 4 , wherein: in the step S 2 of arranging the first adhesive, a plurality of first adhesives in equal amounts are arranged at a plurality of positions on at least one of the first surface and the second surface, and the plurality of positions being separated from each other; the plurality of first adhesives and a plurality of spacers are arranged at intervals when the first surface and the second surface are brought together; and an amount of a corresponding one first adhesive of the plurality of first adhesives arranged at each of the plurality of position on the at least one of the first surface and the second surface is greater than or equal to an amount of a corresponding one second adhesive of the plurality of second adhesives arranged at each of the plurality of positions on the at least one of the first surface and the second surface in step S 12 .
  7. 7 . The chip packaging method according to claim 1 , wherein in the step S 2 of arranging the first adhesive, at least part of the first adhesive is arranged on the spacer.
  8. 8 . The chip packaging method according to claim 2 , wherein the step S 12 comprises: curing the second adhesive for a first time; and detecting whether the cured second adhesive reaches a predetermined height, and in response to that the cured second adhesive fails to reach the predetermined height, replenishing the second adhesive, and performing said curing and said detection again, until the cured second adhesive reaches the predetermined height.
  9. 9 . The chip packaging method according to claim 1 , wherein in the step S 4 of curing the first adhesive, the package substrate and the chip are tightly pressed against each other, the first surface and the second surface being kept parallel to each other during tightly pressing the package substrate and the chip against each other, and the spacer being in contact with the first surface and the second surface.
  10. 10 . The chip packaging method according to claim 2 , wherein in the step S 4 of curing the first adhesive, the package substrate and the chip are tightly pressed against each other, the first surface and the second surface being kept parallel to each other during tightly pressing the package substrate and the chip against each other, and the spacer being in contact with the first surface and the second surface.
  11. 11 . The chip packaging method according to claim 3 , wherein in the step S 4 of curing the first adhesive, the package substrate and the chip are tightly pressed against each other, the first surface and the second surface being kept parallel to each other during tightly pressing the package substrate and the chip against each other, and the spacer being in contact with the first surface and the second surface.
  12. 12 . The chip packaging method according to claim 4 , wherein in the step S 4 of curing the first adhesive, the package substrate and the chip are tightly pressed against each other, the first surface and the second surface being kept parallel to each other during tightly pressing the package substrate and the chip against each other, and the spacer being in contact with the first surface and the second surface.
  13. 13 . The chip packaging method according to claim 5 , wherein in the step S 4 of curing the first adhesive, the package substrate and the chip are tightly pressed against each other, the first surface and the second surface being kept parallel to each other during tightly pressing the package substrate and the chip against each other, and the spacer being in contact with the first surface and the second surface.
  14. 14 . The chip packaging method according to claim 6 , wherein in the step S 4 of curing the first adhesive, the package substrate and the chip are tightly pressed against each other, the first surface and the second surface being kept parallel to each other during tightly pressing the package substrate and the chip against each other, and the spacer being in contact with the first surface and the second surface.
  15. 15 . The chip packaging method according to claim 7 , wherein in the step S 4 of curing the first adhesive, the package substrate and the chip are tightly pressed against each other, the first surface and the second surface being kept parallel to each other during tightly pressing the package substrate and the chip against each other, and the spacer being in contact with the first surface and the second surface.
  16. 16 . The chip packaging method according to claim 8 , wherein in the step S 4 of curing the first adhesive, the package substrate and the chip are tightly pressed against each other, the first surface and the second surface being kept parallel to each other during tightly pressing the package substrate and the chip against each other, and the spacer being in contact with the first surface and the second surface.
  17. 17 . A chip packaging structure, comprising: a package substrate having a first surface; a chip having a second surface, a void layer being formed between the first surface and the second surface; a spacer sandwiched between the first surface and the second surface; and a first adhesive arranged in the void layer, the first surface being adhered to the second surface by the first adhesive, or the first surface being adhered to the second surface through the first adhesive and the spacer, wherein a distribution area of the first adhesive at the second surface is smaller than an area of the second surface.

Description

FIELD The present disclosure relates to a packaging method, and more particularly, to a chip packaging method and a chip packaging structure. BACKGROUND In a chip packaging method in the related technologies, an attachment material is generally used to directly cover whole or part of a chip region. When environmental factors change, such as a chip temperature is too high, a thermal expansion mismatch occurs between a chip and a package, and thus a lateral displacement of the chip with respect to the package occurs. Since a lateral load due to the thermal expansion mismatch cannot be easily released through a lateral displacement of the attachment material and most of the load causes the chip to bend, an optical surface of the chip is deformed. A deformation of the optical surface of the chip leads to an unsatisfying optical quality. For example, for a vehicle, a micro-electro-mechanical system (MEMS) optical scanner is used in a LiDAR to create a real-time 3D map for the vehicle. In use, it is vital that the scanner's effect on the divergence of the light source is kept minimal, which requires the scanner surface to be as flat as possible. However, even with an optically flat MEMS optical scanner die, after packaging, the influence on the divergence can be substantial with conventional die attachment methods (i.e., the packaging process caused die surface deformation). If the MEMS optical scanner obtained through a conventional chip attachment method is designed improperly, temperature variation of the chip causes thermal expansions of both the chip and the package. However, degrees of expansion of both the chip and the package cannot be consistent, which results in stresses and deformations in the chip. Therefore, with the conventional chip attachment method, a beam quality is likely to be seriously affected due to the stresses and the deformations of the chip. In addition to optical MEMS, in many other MEMS devices as well as some semiconductor and integrated circuit devices, the chip is packaged through the conventional attachment method, which causes environment-induced problems such as stresses and deformations during use. Therefore, there is some room for improvement in a packaging method for a chip packaged through attachment. SUMMARY According to an embodiment in a first aspect of the present disclosure, a chip packaging method is provided. The chip packaging method includes: a step S1 of arranging a spacer on at least one of a first surface of a package substrate and a second surface of a chip, a step S2 of arranging a first adhesive on at least one of the first surface, the second surface, or the spacer, a step S3 of bringing together the first surface of the package substrate and the second surface of the chip, to sandwich the spacer between the first surface and the second surface, and adhere the first surface to the second surface by the first adhesive, or adhere the first surface to the second surface by the first adhesive and the spacer, a distribution area of the first adhesive at the second surface is smaller than an area of the second surface, and S4, curing the first adhesive. According to an embodiment in a second aspect of the present disclosure, a chip packaging structure is provided. The chip packaging structure applies the above-mentioned chip packaging method and includes: a package substrate having a first surface. A chip having a second surface, a void layer being formed between the first surface and the second surface; a spacer sandwiched between the first surface and the second surface. The chip packaging structure further includes a first adhesive arranged in the void layer, the first surface being adhered to the second surface by the first adhesive, or the first surface and the second surface being adhered to the first adhesive by the spacer. A distribution area of the first adhesive at the second surface is smaller than an area of the second surface. BRIEF DESCRIPTION OF THE DRAWINGS The above and/or additional aspects and advantages of the present disclosure will become more apparent and more understandable from the following description of embodiments taken in conjunction with the accompanying drawings. FIG. 1 is a schematic view of an adhesive connection applied between a chip and a package substrate in the related art. FIG. 2 is a flowchart illustrating a chip packaging method according to an embodiment of the present disclosure. FIG. 3 is a schematic view of arranging a spacer at a first surface of a package substrate according to some embodiments of the present disclosure. FIG. 4 is a schematic view of arranging a first adhesive at the first surface of the package substrate according to the embodiments illustrated in FIG. 3 after arranging the spacer at the first surface of the package substrate. FIG. 5 is a schematic view of attaching a chip to the package substrate according to the embodiments illustrated in FIG. 4. FIG. 6 is a schematic view of sequentially arranging