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US-20260130256-A1 - FLUX CLEANING JIG

US20260130256A1US 20260130256 A1US20260130256 A1US 20260130256A1US-20260130256-A1

Abstract

One embodiment of the present disclosure provides a flux cleaning jig including a lower jig on which a substrate to which a plurality of semiconductor chips is attached by conductive bumps is configured to be seated, and an upper jig disposed on the lower jig, and having a plurality of openings in which at least a portion on the semiconductor chips are configured to be disposed, the upper jig including a partition disposed between adjacent openings from among the plurality of openings, and a frame surrounding the partition, in which the partition includes a section in which a width increases in a direction from the upper jig toward the lower jig.

Inventors

  • Soonchul LEE

Assignees

  • SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date
20260507
Application Date
20250801
Priority Date
20241104

Claims (20)

  1. 1 . A flux cleaning jig comprising: a lower jig on which a substrate, to which a plurality of semiconductor chips is attached by conductive bumps, is configured to be seated; and an upper jig disposed on the lower jig, the upper jig having a plurality of openings in which at least a portion of the semiconductor chips are configured to be disposed, the upper jig comprising a partition disposed between adjacent openings from among the plurality of openings, and the upper jig including a frame surrounding the partition, wherein the partition comprises a section in which a width increases in a first direction from the upper jig toward the lower jig.
  2. 2 . The flux cleaning jig of claim 1 , wherein: a width of each opening from among the plurality of openings is larger than a width of each semiconductor chip from among the plurality of semiconductor chips.
  3. 3 . The flux cleaning jig of claim 2 , wherein: the partition is spaced apart from each semiconductor chip from among the plurality of semiconductor chips.
  4. 4 . The flux cleaning jig of claim 3 , wherein: a gap between the partition and each semiconductor chip from among the plurality of semiconductor chips is 100 μm or more.
  5. 5 . The flux cleaning jig of claim 1 , wherein: a thickness of the partition in the first direction is larger than a thickness of each semiconductor chip from among the plurality of semiconductor chips in the first direction.
  6. 6 . The flux cleaning jig of claim 1 , wherein: the partition has a maximum width in a second direction perpendicular to the first direction at a surface of the partition facing the lower jig.
  7. 7 . The flux cleaning jig of claim 1 , wherein: the lower jig comprises: a main body; and a magnet embedded in the main body in a region that overlaps the frame when viewed in a plan view, and the upper jig comprises a magnetic material.
  8. 8 . The flux cleaning jig of claim 1 , wherein: the lower jig includes a protrusion, and the frame has a hole into which the protrusion is configured to be inserted.
  9. 9 . The flux cleaning jig of claim 1 , wherein: the substrate is positioned below the plurality of openings.
  10. 10 . The flux cleaning jig of claim 1 , wherein: a thickness of the section of the partition, in which the width increases in the first direction, is larger than a thickness of the remaining section, in which the width is constant or decreases in the first direction.
  11. 11 . A flux cleaning jig comprising: a lower jig on which a substrate, to which a plurality of semiconductor chips is attached by conductive bumps, is configured to be seated; an upper jig disposed on the lower jig, the upper jig having a plurality of openings in which at least a portion of the semiconductor chips are disposed, the upper jig comprising a partition disposed between adjacent openings from among the plurality of openings, and the upper jig including a frame surrounding the partition; and a plurality of first support pillars coupled to a lower surface of the upper jig and configured to press the substrate seated on the lower jig.
  12. 12 . The flux cleaning jig of claim 11 , wherein: each of the plurality of first support pillars comprises a magnet, and at least one of the lower jig and the upper jig comprises a magnetic material.
  13. 13 . The flux cleaning jig of claim 11 , wherein: the plurality of first support pillars are arranged to surround each semiconductor chip from among the plurality of semiconductor chips.
  14. 14 . The flux cleaning jig of claim 11 , further comprising: a second support pillar disposed between the lower jig and the frame, the second support pillar connecting the lower jig to the upper jig.
  15. 15 . The flux cleaning jig of claim 14 , wherein: the second support pillar comprises a magnet, and at least one of the lower jig and the upper jig comprises a magnetic material.
  16. 16 . The flux cleaning jig of claim 14 , wherein: when viewed in a plan view, the second support pillar does not overlap a region of the lower jig where the substrate is configured to be seated.
  17. 17 . The flux cleaning jig of claim 16 , wherein: the lower jig has a groove into which one end of the second support pillar is configured to be inserted.
  18. 18 . The flux cleaning jig of claim 16 , wherein: the frame has a groove into which one end of the second support pillar is configured to be inserted.
  19. 19 . A flux cleaning jig comprising: a lower jig on which a substrate, to which a plurality of semiconductor chips is attached by conductive bumps, is configured to be seated; an upper jig disposed on the lower jig, the upper jig having a plurality of openings in which at least a portion of the semiconductor chips are configured to be disposed, the upper jig comprising a partition disposed between adjacent openings from among the plurality of openings, and the upper jig including a frame surrounding the partition; and a plurality of support pillars coupled to a lower surface of the upper jig, the plurality of support pillars being configured to press the substrate seated on the lower jig, wherein the partition comprises a section in which a width increases in a direction from the upper jig toward the lower jig.
  20. 20 . The flux cleaning jig of claim 19 , wherein: each of the plurality of support pillars comprises a magnet, and at least one of the lower jig and the upper jig comprises a magnetic material.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0154524 filed in the Korean Intellectual Property Office on Nov. 4, 2024, the entire contents of which are incorporated herein by reference. BACKGROUND OF THE INVENTION (a) Field of the Invention The present disclosure relates to a flux cleaning jig. (b) Description of the Related Art A flip chip bonding technology has been known in a semiconductor package industrial field as a technology for attaching solder bumps on semiconductor chips, aligning the semiconductor chips, to which the solder bumps are attached, on a substrate, and then connecting the semiconductor chips to the substrate by performing a reflow process at a high temperature. The flip chip bonding technology is advantageous in enabling high-speed data transmission and miniaturization and high-performance of products. During flip chip bonding, flux is used to smoothly bond the solder bump to the substrate. In case that a flux residue remains after the reflow process is completed, there may occur a problem in that a bonding force between a surface of the semiconductor chip and an EMC deteriorates, and electrical reliability deteriorates. SUMMARY OF THE INVENTION The present disclosure provides a jig capable of improving flux cleaning efficiency. According to an embodiment, a flux cleaning jig includes: a lower jig on which a substrate to which a plurality of semiconductor chips is attached by conductive bumps is seated; and an upper jig disposed on the substrate, which is seated on the lower jig, and having a plurality of openings in which at least a portion on the semiconductor chips are disposed, the upper jig including partition portion disposed between the plurality of openings, and a frame configured to surround the partition portion, in which the partition portion includes a section in which a width increases in a first direction from the upper jig toward the lower jig. According to another embodiment, a flux cleaning jig includes: a lower jig on which a substrate to which a plurality of semiconductor chips is attached by conductive bumps is seated; an upper jig disposed on the substrate, which is seated on the lower jig, and having a plurality of openings in which at least a portion on the semiconductor chips are disposed, the upper jig including partition portion disposed between the plurality of openings, and a frame configured to surround the partition portion; and a plurality of first support structures coupled to a lower surface of the upper jig and configured to press the substrate seated on the lower jig. According to another embodiment, a flux cleaning jig includes: a lower jig on which a substrate to which a plurality of semiconductor chips is attached by conductive bumps is seated; an upper jig disposed on the substrate, which is seated on the lower jig, and having a plurality of openings in which at least a portion on the semiconductor chips are disposed, the upper jig including partition portion disposed between the plurality of openings, and a frame configured to surround the partition portion; and a plurality of support structures coupled to a lower surface of the upper jig and configured to press the substrate seated on the lower jig, in which the partition portion includes a section in which a width increases in a direction from the upper jig toward the lower jig. According to another embodiment, a method of cleaning a substrate using a flux cleaning jig includes placing a substrate on a lower jig of the flux cleaning jig, the substrate having a semiconductor chip attached thereto; placing an upper jig of the flux cleaning jig on the substrate such that the semiconductor chip is positioned within an opening formed in the upper jig; applying a cleaning fluid to the substrate and the semiconductor chip, wherein walls of the opening formed in the upper jig are inclined such that the cleaning fluid flows toward the semiconductor chip. The semiconductor chip may be attached to the substrate using conductive bumps, and in the step of applying the cleaning fluid, the walls of the opening formed in the upper jig may direct the cleaning fluid toward the conductive bumps. A width of the opening formed in the upper jig may be larger than a width of the semiconductor chip. A height of the walls of the opening formed in the upper jig may be larger than a sum of a height of the semiconductor chip and a height of the conductive bumps. According to one or more aspects of the present disclosure, it is possible to provide the jig capable of improving the flux cleaning efficiency. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a view illustrating a state before an upper jig and a lower jig of a flux cleaning jig according to an embodiment are coupled. FIG. 2 is a top plan view of the lower jig illustrated in FIG. 1. FIG. 3 is a top plan view of the upper jig illustrated in FIG. 1. FIG. 4 is a partially enlarged cro