US-20260130259-A1 - SEMICONDUCTOR DEVICE

Abstract

Provided is a semiconductor device with a configuration capable of ensuring insulation properties between terminals having different potentials and arranged with an insulating layer interposed. The semiconductor device includes: a first terminal; a second terminal having a part opposed to the first terminal and another part provided with a first opening not opposed to the first terminal; and an insulating layer including a body part interposed between the first terminal and the second terminal opposed to each other and a first protrusion connected to the body part and inserted to the first opening.

Inventors

• Naoyuki Kanai
• Ryoichi Kato

Assignees

• FUJI ELECTRIC CO., LTD.

Dates

Publication Date

20260507

Application Date

20260105

Priority Date

20240311

Claims (15)

1. 1 . A semiconductor device comprising: a first terminal: a second terminal having a part opposed to the first terminal and another part provided with a first opening not opposed to the first terminal; and an insulating layer including a body part interposed between the first terminal and the second terminal opposed to each other, and a first protrusion connected to the body part and inserted to the first opening.
2. 2 . The semiconductor device of claim 1 , wherein the second terminal includes: a first flat part having at least a part opposed to the first terminal; and a first connection part bent from the first flat part so as to be connected to each other.
3. 3 . The semiconductor device of claim 2 , wherein the first opening is provided in the first connection part.
4. 4 . The semiconductor device of claim 2 , wherein a part of the first flat part is opposed to the first terminal, and another part of the first flat part not opposed to the first terminal is provided with the first opening, and the first protrusion is bent from the body part so as to be inserted to the first opening.
5. 5 . The semiconductor device of claim 2 , wherein the second terminal further includes a second connection part bent from the first flat part so as to be connected to each other on an opposite side of the first connection part, and provided with a second opening, and the insulating layer further includes a second protrusion connected to the body part and inserted to the second opening.
6. 6 . The semiconductor device of claim 1 , wherein a part of the first terminal is opposed to the second terminal, and another part of the first terminal not opposed to the second terminal is provided with a second opening, and the insulating layer further includes a second protrusion connected to the body part and inserted to the second opening.
7. 7 . The semiconductor device of claim 6 , wherein the first terminal includes: a second flat part having at least a part opposed to the second terminal; and a third connection part bent from the second flat part so as to be connected to each other.
8. 8 . The semiconductor device of claim 7 , wherein the third connection part is provided with the second opening.
9. 9 . The semiconductor device of claim 7 , wherein a part of the second flat part is opposed to the second terminal, and another part of the second flat part is provided with the second opening, and the second protrusion is bent so as to be inserted to the second opening.
10. 10 . The semiconductor device of claim 5 , wherein the first protrusion and the second protrusion are located so as to be opposed to each other with the body part interposed.
11. 11 . The semiconductor device of claim 5 , wherein the first protrusion and the second protrusion are shifted from each other so as not to be opposed to each other with the body part interposed.
12. 12 . The semiconductor device of claim 1 , wherein the first protrusion is provided with a catch part.
13. 13 . The semiconductor device of claim 1 , wherein a tip part of the first protrusion projects from the first opening and is further bent.
14. 14 . The semiconductor device of claim 1 , wherein a length of the first protrusion is greater than or equal to a thickness of the second terminal.
15. 15 . The semiconductor device of claim 1 , further comprising: an insulated circuit substrate provided with the first terminal and the second terminal on a top surface side; a semiconductor chip provided on the top surface side of the insulated circuit substrate and electrically connected to the first terminal and the second terminal; and a sealing resin provided to seal the insulated circuit substrate and the semiconductor chip.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is a Continuation of PCT Application No. PCT/JP2024/045840, filed on Dec. 25, 2024, and claims the priority of Japanese Patent Application No. 2024-037394, filed on Mar. 11, 2024, the content of which are incorporated herein by reference. TECHNICAL FIELD The present invention relates to semiconductor devices (power semiconductor modules). BACKGROUND ART JP2010-157565A discloses a configuration including three electrode-leading terminals stacked together with insulating resin sheets interposed so as to implement a five-layer structure, in which positioning pins are inserted to two stacking holes provided in the five-layer structure so as to achieve mutual positioning between the respective layers. JP2023-088055A discloses a configuration including an insulating sheet having a first main surface and a second main surface, a first terminal in a shape of a plate provided to face the first main surface of the insulating sheet and including a first protruding portion protruding outward from the first main surface of the insulating sheet, and a second terminal in a shape of a plate provided to face the second main surface of the insulating sheet and including a second protruding portion protruding outward from the second main surface of the insulating sheet side by side with the first protruding portion, wherein a first recessed opening portion is provided at a position of the first protruding portion intersecting an end portion of the insulating sheet by concaving a side surface of the first protruding portion facing the second protruding portion in a direction away from the second protruding portion. JP2019-207922A discloses a configuration including main terminals having projecting portions projecting outward from a sealing resin body, the projecting portions having facing portions provided with plate surfaces arranged separately to face each other so as to mutually cancel out magnetic fluxes caused during a flow of main currents and having non-facing portions at which the respective plate surfaces do not face each other. JP2006-086438A discloses a configuration including a metal die for resin molding preliminarily provided with positioning pins, wherein the guide holes in the insulating sheet are formed to have a sufficiently smaller size than those in respective plus and minus busbars, while the positioning pins are provided with steps conforming to the corresponding sizes of the diameters of the respective guide holes, so as to increase the accuracy of positioning when the positioning pins are sequentially inserted into the respective guide holes of the plus busbar, the insulating sheet, and the minus busbar. JP2005-065414A discloses a configuration including a positive-electrode conductor, an insulating sheet, and a negative-electrode conductor laminated together, and including insulating caps arranged between the positive-electrode conductor and the insulating sheet, each insulating cap provided with a flange for ensuring a creepage distance and barrier parts for ensuring a space distance, wherein the positive-electrode conductor is provided with holes having a size set only necessary for the insertion of the barrier parts of the insulating caps, and the negative-electrode conductor is provided with holes having a size set only necessary for the penetration and positioning of the barrier parts, so as to greatly enhance the effect of reducing inductance obtained by proximity of opposing currents. SUMMARY OF THE INVENTION Technical Problem Conventional power semiconductor devices developed recently have a configuration in which terminals having different potentials are arranged to be opposed to each other (laminated together) with an insulating layer interposed in order to achieve a reduction in inductance. Such a configuration, however, has a problem of not easy positioning between the respective terminals and the insulating layer, which impedes the effect of ensuring the insulation properties between the respective terminals. In view of the foregoing problems, the present disclosure provides a semiconductor device having a configuration capable of ensuring insulation properties between terminals having different potentials stacked together with an insulating layer interposed. Solution to Problem An aspect of the present disclosure inheres in a semiconductor device including: a first terminal; a second terminal having a part opposed to the first terminal and another part provided with a first opening not opposed to the first terminal; and an insulating layer including a body part interposed between the first terminal and the second terminal opposed to each other, and a first protrusion connected to the body part and inserted to the first opening. In the aspect of the present disclosure, the second terminal may include: a first flat part having at least a part opposed to the first terminal; and a first connection part bent from the first flat part so as