US-20260130260-A1 - SEMICONDUCTOR DEVICE

US20260130260A1US 20260130260 A1US20260130260 A1US 20260130260A1US-20260130260-A1

Abstract

A semiconductor device includes a resin housing, a substrate, a plurality of semiconductor elements, and a signal terminal. Each of the semiconductor elements has a first main electrode on a first surface, a second main electrode and a pad on a second surface opposite to the first surface. The first main electrodes are joined to a wiring of the substrate. The signal terminal is inserted in the housing, and electrically connected to the pads. The signal terminal includes a branch terminal. The branch terminal has a single first connection portion projecting from the housing to be connected to an external device, a plurality of second connection portions exposed from the housing and individually connected to the pads having a same function of the semiconductor elements, and a coupling portion disposed within the housing and electrically connecting the first connection portion and the second connection portions.

Inventors

Kenji Onoda
Masayoshi Nishihata
Takahiro Hirano

Assignees

DENSO CORPORATION

Dates

Publication Date: 20260507
Application Date: 20260102
Priority Date: 20230705

Claims (7)

1 . A semiconductor device comprising: a resin housing; a substrate having a wiring; a plurality of semiconductor elements each having a first main electrode disposed on a first surface, a second main electrode disposed on a second surface opposite to the first surface, and a pad disposed on the second surface, the first main electrodes being commonly joined to the wiring; and a signal terminal inserted in the housing, and electrically connected to the pads, wherein the signal terminal includes a branch terminal, and the branch terminal has a single first connection portion that projects from the housing to be connected to an external device, a plurality of second connection portions that are exposed from the housing and individually connected to the pads of the plurality of semiconductor elements, the pads having a same function, and a coupling portion that is disposed within the housing and electrically connects the first connection portion and the plurality of second connection portions.
2 . The semiconductor device according to claim 1 , wherein the plurality of semiconductor elements are aligned in a first direction on the wiring of the substrate, the semiconductor device further comprising: a main terminal aligned with the plurality of semiconductor elements in a second direction orthogonal to the first direction, and connected to a central region of the wiring in the first direction, wherein the plurality of second connection portions are disposed on opposite sides of the main terminal in the first direction.
3 . The semiconductor device according to claim 2 , wherein the wiring of the substrate is a main circuit wiring, the substrate has a signal wiring that is disposed separately from the main circuit wiring and electrically relays the pads and the signal terminal, the signal wiring is provided to correspond to the second connection portions, and includes a plurality of divided wirings that are individually connected to the pads having the same function, and the plurality of divided wirings are disposed between the plurality of semiconductor elements and the second connection portions in the second direction, and are disposed on opposite sides of the main terminal in the first direction.
4 . The semiconductor device according to claim 2 , wherein the plurality of semiconductor elements are a plurality of first semiconductor elements, and provide a lower arm of an upper and lower arm circuit, the semiconductor device further comprising: a plurality of second semiconductor elements providing an upper arm of the upper and lower arm circuit, the plurality of first semiconductor elements and the plurality of second semiconductor elements are disposed side by side in the second direction, and the main terminal is an output terminal.
5 . The semiconductor device according to claim 4 , wherein the output terminal is inserted in the housing.
6 . The semiconductor device according to claim 5 , wherein the output terminal is provided with a shunt resistor for a current sensing.
7 . The semiconductor device according to claim 5 , further comprising: a current sensor core that is inserted in the housing, and disposed on a periphery of the output terminal.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS The present application is a continuation application of International Patent Application No. PCT/JP2024/020602 filed on Jun. 6, 2024, which designated the U.S. and claims the benefit of priority from Japanese Patent Application No. 2023-110770 filed on Jul. 5, 2023. The entire disclosures of all of the above applications are incorporated herein by reference. TECHNICAL FIELD The present disclosure herein relates to a semiconductor device. BACKGROUND JP 2019-67970 A discloses a semiconductor device. Contents of the description of JP 2019-67970 A are incorporated herein by reference as a description of technical elements in this description. SUMMARY According to an aspect of the present disclosure, a semiconductor device includes a resin housing, a substrate, a plurality of semiconductor elements, and a signal terminal. The substrate has a wiring. Each of the plurality of semiconductor elements has a first main electrode disposed on a first surface, a second main electrode disposed on a second surface opposite to the first surface, and a pad disposed on the second surface. The first main electrodes are commonly joined to the wiring. The signal terminal is inserted in the housing, and is electrically connected to the pads. The signal terminal may include a branch terminal. The branch terminal may have a single first connection portion that projects from the housing to be connected to an external device, a plurality of second connection portions that are exposed from the housing and individually connected to the pads of the plurality of semiconductor elements, the pads having a same function, and a coupling portion that is disposed within the housing and electrically connects the first connection portion and the plurality of second connection portions. BRIEF DESCRIPTION OF DRAWINGS Features and advantages of the present disclosure will become more apparent from the following detailed description made with reference to the accompanying drawings. FIG. 1 is a diagram illustrating a circuit configuration of a power conversion device to which a semiconductor device according to a first embodiment is applied. FIG. 2 is a perspective view illustrating an example of a semiconductor module. FIG. 3 is a plan view of the semiconductor module. FIG. 4 is a cross-sectional view taken along a line IV-IV in FIG. 3. FIG. 5 is a plan view illustrating an example of the semiconductor device. FIG. 6 is a plan view illustrating a wiring pattern of a substrate. FIG. 7 is a cross-sectional view taken along a line VII-VII in FIG. 5. FIG. 8 is a cross-sectional view illustrating another example of the connection structure between a capacitor and the substrate. FIG. 9 is a cross-sectional view illustrating still another example of the connection structure between the capacitor and the substrate. FIG. 10 is a cross-sectional view illustrating still another example of the connection structure between the capacitor and the substrate. FIG. 11 is a circuit diagram illustrating a verification model. FIG. 12 is a diagram illustrating a verification result. FIG. 13 is a diagram illustrating a temperature distribution. FIG. 14 is a diagram illustrating disposition of a current path formed by a snubber circuit. FIG. 15 is a plan view illustrating a modification example. FIG. 16 is a plan view illustrating another modification example. FIG. 17 is a plan view illustrating still another modification example. FIG. 18 is a plan view illustrating a semiconductor element in a semiconductor device according to a second embodiment. FIG. 19 is a cross-sectional view taken along a line XIX-XIX in FIG. 18. FIG. 20 is a partial cross-sectional view of the semiconductor device and a semiconductor module. FIG. 21 is a plan view illustrating an example of a connection structure between a clip and the semiconductor element. FIG. 22 is a cross-sectional view taken along a line XXII-XXII in FIG. 21. FIG. 23 is a plan view illustrating another example of the connection structure between the clip and the semiconductor element. FIG. 24 is a perspective view illustrating the clip. FIG. 25 is a plan view illustrating another example of the clip. FIG. 26 is a plan view illustrating still another example of the clip. FIG. 27 is a cross-sectional view illustrating still another example of the clip. FIG. 28 is a plan view illustrating still another example of the clip. FIG. 29 is a plan view illustrating still another example of the connection structure between the clip and the semiconductor element. FIG. 30 is a cross-sectional view taken along a line XXX-XXX in FIG. 29. FIG. 31 is a plan view illustrating still another example of the clip. FIG. 32 is a plan view illustrating still another example of the clip. FIG. 33 is a plan view illustrating still another example of the clip. FIG. 34 is a plan view illustrating still another example of the clip. FIG. 35 is a plan view illustrating still another example of the clip. FIG. 36 is a p