US-20260130261-A1 - SEMICONDUCTOR DEVICE

US20260130261A1US 20260130261 A1US20260130261 A1US 20260130261A1US-20260130261-A1

Abstract

A semiconductor device includes at least one semiconductor element, a metal plate and a solder. The semiconductor element includes a semiconductor substrate having an element region, a main electrode disposed at a position overlapping with the element region on one surface of the semiconductor substrate, a signal line disposed at a position overlapping with the element region on the one surface and different from the position of the main electrode, and an insulating film covering the signal line. The metal plate has a joint portion to the main electrode. The solder is interposed between the main electrode and the joint portion and joins the main electrode and the metal plate. The joint portion is disposed to avoid the signal line.

Inventors

Takahiro Hirano
Masayuki Kamiya

Assignees

DENSO CORPORATION

Dates

Publication Date: 20260507
Application Date: 20260102
Priority Date: 20230705

Claims (12)

1 . A semiconductor device comprising: at least one semiconductor element that includes a semiconductor substrate having an element region, a main electrode disposed at a position overlapping with the element region on one surface of the semiconductor substrate, a signal line disposed at a position overlapping with the element region on the one surface and being different from the position of the main electrode, and an insulating film covering the signal line and interposed by the main electrode in a plan view in a thickness direction of the semiconductor substrate; a metal plate having a joint portion to the main electrode; and a solder interposed between the main electrode and the joint portion of the metal plate and joining the main electrode and the metal plate, wherein the joint portion is disposed to avoid the signal line.
2 . The semiconductor device according to claim 1 , wherein the metal plate has a plurality of the joint portions for a same semiconductor element.
3 . The semiconductor device according to claim 2 , wherein the joint portions for the same semiconductor element are branched portions.
4 . The semiconductor device according to claim 3 , wherein the metal plate has a bridge portion connected to the joint portions that are adjacent to each other at a position farther away from the one surface than the joint portions.
5 . The semiconductor device according to claim 1 , wherein the joint portion includes a plurality of first joint portions, and the metal plate has a second joint portion which is different from the plurality of first joint portions.
6 . The semiconductor device according to claim 5 , further comprising: a substrate having an insulating base material and a wiring disposed on the insulating base material, wherein the at least one semiconductor element is disposed on a surface of the substrate on which the wiring is disposed, and the second joint portion is connected to the wiring.
7 . The semiconductor device according to claim 5 , wherein the main electrode is a first main electrode, and the at least one semiconductor element includes a second main electrode disposed on a rear surface of the semiconductor substrate opposite to the one surface, the semiconductor device further comprising: a metal member; and a sintered member interposed between the second main electrode and the metal member and joining the second main electrode and the metal member.
8 . The semiconductor device according to claim 5 , wherein the semiconductor element has a pad disposed on the one surface of the semiconductor substrate and electrically connected to the signal line, the semiconductor device further comprising: a signal terminal; a bonding wire electrically connecting the pad and the signal terminal; and a gel that seals the at least one semiconductor element, the metal plate, a part of the signal terminal, and the bonding wire, wherein the metal plate is formed with a through hole at a portion connecting the plurality of first joint portions and the second joint portion.
9 . The semiconductor device according to claim 5 , further comprising: a sealing body that seals the at least one semiconductor element and the metal plate, wherein the metal plate has an inclined shape at a position connecting the plurality of first joint portions and the second joint portion, the inclined shape being inclined with respect to a direction in which the plurality of first joint portions and the second joint portion are aligned.
10 . The semiconductor device according to claim 5 , wherein the at least one semiconductor element includes a plurality of the semiconductor elements, one of the plurality of first joint portions is joined to one of the plurality of semiconductor elements, and another of the plurality of first joint portions is joined to another of the plurality of semiconductor elements.
11 . The semiconductor device according to claim 10 , wherein the metal plate has a coupling portion connecting the plurality of first joint portions and the second joint portion, and the coupling portion has a shape that branches from the second joint portion to the plurality of first joint portions to avoid a region between the plurality of semiconductor elements.
12 . The semiconductor device according to claim 10 , wherein the metal plate has a coupling portion connecting the plurality of first joint portions and the second joint portion, and the coupling portion has a shape that branches from the second joint portion to the plurality of first joint portions from a region between the plurality of semiconductor elements.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS The present application is a continuation application of International Patent Application No. PCT/JP2024/020605 filed on Jun. 6, 2024, which designated the U.S. and claims the benefit of priority from Japanese Patent Application No. 2023-110768 filed on Jul. 5, 2023 and Japanese Patent Application No. 2024-070077 filed on Apr. 23, 2024. The entire disclosures of all of the above applications are incorporated herein by reference. TECHNICAL FIELD The present disclosure herein relates to a semiconductor device. BACKGROUND JP 2022-130702 A discloses a semiconductor device including a semiconductor element and a metal plate which is soldered and joined to a main electrode of the semiconductor element. Contents of the description of JP 2022-130702 A are incorporated herein by reference as a description of technical elements in this description. SUMMARY According to an aspect of the disclosure, a semiconductor device includes at least one semiconductor element, a metal plate and a solder. The at least one semiconductor element includes a semiconductor substrate having an element region, a main electrode disposed at a position overlapping with the element region on one surface of the semiconductor substrate, a signal line disposed at a position overlapping with the element region on the one surface and being different from the position of the main electrode, and an insulating film covering the signal line. The metal plate has a joint portion to the main electrode. The solder is interposed between the main electrode and the joint portion of the metal plate and joins the main electrode and the metal plate. The joint portion is disposed to avoid the signal line. BRIEF DESCRIPTION OF DRAWINGS Features and advantages of the present disclosure will become more apparent from the following detailed description made with reference to the accompanying drawings. FIG. 1 is a diagram illustrating a circuit configuration of a power conversion device to which a semiconductor device according to a first embodiment is applied. FIG. 2 is a perspective view illustrating an example of a semiconductor module. FIG. 3 is a plan view of the semiconductor module. FIG. 4 is a cross-sectional view taken along a line IV-IV in FIG. 3. FIG. 5 is a plan view illustrating an example of the semiconductor device. FIG. 6 is a plan view illustrating a wiring pattern of a substrate. FIG. 7 is a cross-sectional view taken along a line VII-VII in FIG. 5. FIG. 8 is a cross-sectional view illustrating another example of the connection structure between a capacitor and the substrate. FIG. 9 is a cross-sectional view illustrating still another example of the connection structure between the capacitor and the substrate. FIG. 10 is a cross-sectional view illustrating still another example of the connection structure between the capacitor and the substrate. FIG. 11 is a circuit diagram illustrating a verification model. FIG. 12 is a diagram illustrating a verification result. FIG. 13 is a diagram illustrating a temperature distribution. FIG. 14 is a diagram illustrating disposition of a current path formed by a snubber circuit. FIG. 15 is a plan view illustrating a modification example. FIG. 16 is a plan view illustrating another modification example. FIG. 17 is a plan view illustrating still another modification example. FIG. 18 is a plan view illustrating a semiconductor element in a semiconductor device according to a second embodiment. FIG. 19 is a cross-sectional view taken along a line XIX-XIX in FIG. 18. FIG. 20 is a partial cross-sectional view of the semiconductor device and a semiconductor module. FIG. 21 is a plan view illustrating an example of a connection structure between a clip and the semiconductor element. FIG. 22 is a cross-sectional view taken along a line XXII-XXII in FIG. 21. FIG. 23 is a plan view illustrating another example of the connection structure between the clip and the semiconductor element. FIG. 24 is a perspective view illustrating the clip. FIG. 25 is a plan view illustrating another example of the clip. FIG. 26 is a plan view illustrating still another example of the clip. FIG. 27 is a cross-sectional view illustrating still another example of the clip. FIG. 28 is a plan view illustrating still another example of the clip. FIG. 29 is a plan view illustrating still another example of the connection structure between the clip and the semiconductor element. FIG. 30 is a cross-sectional view taken along a line XXX-XXX in FIG. 29. FIG. 31 is a plan view illustrating still another example of the clip. FIG. 32 is a plan view illustrating still another example of the clip. FIG. 33 is a plan view illustrating still another example of the clip. FIG. 34 is a plan view illustrating still another example of the clip. FIG. 35 is a plan view illustrating still another example of the clip. FIG. 36 is a plan view illustrating still another example of the clip. FIG. 37 is a plan view illustrating still