US-20260130262-A1 - CONNECTIVITY METHOD AND STRUCTURE FOR 3D-CHIPLET STACKS FOR POWER; GROUND; AND LIMITED SIGNALS

Abstract

A device may include a plurality of chiplets stacked on top of each other. Each chiplet includes: one or more electronic components; a plurality of connections electrically connecting the one or more electronic components, the plurality of connections formed in one or more metal layers; main surfaces and side surfaces, wherein the main surfaces of adjacent chiplets of the plurality of chiplets face each other. The device may further include an electrically conductive connection formed on at least one side surface of at least one chiplet of the plurality of chiplets to electrically connect one or more connections of the plurality of connections of one or more chiplets of the plurality of chiplets.

Inventors

• Stephen Morein
• Casey THIELEN
• Terry William GILMORE

Assignees

• INTEL CORPORATION

Dates

Publication Date

20260507

Application Date

20251219

Claims (20)

1. 1 . A device, comprising, a plurality of chiplets stacked on top of each other, wherein each chiplet comprises: one or more electronic components; a plurality of connections electrically connecting the one or more electronic components, the plurality of connections formed in one or more metal layers; main surfaces and side surfaces, wherein the main surfaces of adjacent chiplets of the plurality of chiplets face each other; an electrically conductive connection formed on at least one side surface of at least one chiplet of the plurality of chiplets to electrically connect one or more connections of the plurality of connections of one or more chiplets of the plurality of chiplets.
2. 2 . The device of claim 1 , wherein the electrically conductive connection comprises a contact pad electrically connected to one or more connections of the plurality of connections of one or more chiplets of the plurality of chiplets.
3. 3 . The device of claim 2 , wherein the contact pad is electrically connected to one or more electronic components via the one or more connections to provide electrical power to the one or more electronic components.
4. 4 . The device of claim 2 , wherein the contact pad is electrically connected to one or more electronic components via the one or more connections to provide at least one of the following group to the one or more electronic components: an electrical reference potential; a ground potential; a test signal; a functional signal; and a debug signal.
5. 5 . The device of claim 3 , wherein the contact pad is configured as a general purpose input output interface.
6. 6 . The device of claim 1 , wherein the electrically conductive connection comprises a bus bar electrically connected to one or more connections of the plurality of connections of one or more chiplets of the plurality of chiplets.
7. 7 . The device of claim 6 , wherein the bus bar is electrically connected to one or more electronic components via the one or more connections to provide at least one of the following group to the one or more electronic components: electrical power; an electrical reference potential; a ground potential; a test signal; a functional signal; and a debug signal.
8. 8 . The device of claim 6 , wherein the bus bar is configured as a general purpose input output interface.
9. 9 . The device of claim 1 , further comprising: a substrate; wherein the plurality of chiplets are disposed over the substrate; wherein the substrate is electrically connected to the electrically conductive connection.
10. 10 . The device of claim 9 , wherein the substrate comprises a grounding structure electrically coupled to the electrically conductive connection.
11. 11 . The device of claim 1 , further comprising: a power source electrically coupled to the electrically conductive connection.
12. 12 . The device of claim 1 , further comprising: encapsulating material at least partially encapsulating the plurality of chiplets and the electrically conductive connection.
13. 13 . The device of claim 1 , wherein the one or more electronic components comprise at least one of the following components: a logic circuit, e.g. a processor; a memory circuit.
14. 14 . The device of claim 1 , wherein the electrically conductive connection comprises a portion formed on an outer main surface of a topmost chiplet or bottommost chiplet of the plurality of chiplets.
15. 15 . A method of manufacturing a device, the method comprising, forming a layer stack comprising a plurality of layers of electrically conductive material on one or more side surfaces of one or more carriers, each carrier comprising: one or more electronic components: a plurality of connections electrically connecting the one or more electronic components, the plurality of connections formed in one or more metal layers; main surfaces and side surfaces; wherein the one or more layers of electrically conductive material are electrically coupled to the one or more connections of the plurality of connections of one or more carriers; forming one or more openings through the outermost layer of the layer stack; removing a portion of the layer stack below the opening using the outermost layer as a mask to expose a portion of a side surface of the one or more carriers so that a remaining portion of the layer stack forms an electrically conductive connection to electrically connect the one or more connections of the plurality of connections of one or more carriers.
16. 16 . The method of claim 15 , wherein the one or more carriers comprise a plurality of carriers stacked on top of each other; wherein the main surfaces of adjacent carriers of the plurality of chiplets face each other.
17. 17 . The method of claim 15 , wherein the one or more carriers comprise one or more chiplets,
18. 18 . The method of claim 15 , wherein the plurality of metal layers comprises a metal selected from a group of metals consisting of: copper; nickel; platinum; and gold.
19. 19 . The method of claim 15 , wherein the one or more openings are formed such that some electrically conductive material of the layer stack remains between the one or more openings and the one or more side surfaces of one or more carriers.
20. 20 . The method of claim 15 , wherein the removing the portion of the layer stack below the opening comprises wet etching some electrically conductive material of the layer stack using the outermost layer as a mask to expose a portion of a side surface of the one or more carriers.

Description

CROSS-REFERENCE TO RELATED APPLICATION Priority is claimed as nonprovisional of U.S. 63/827,012 filed on Jun. 20, 2025. BACKGROUND With a 3D chiplet stack, power and ground connections need to be created for every die. That takes precious connections from the base of the 3D chiplet stack that could otherwise support data bandwidth and signaling in general. If the 3D chiplet stack is rotated on-edge, the connections to the substrate base are likely more difficult to support from all the chiplets in the stack, and power especially can suffer from the longer physical length or restricted width of the connections. BRIEF DESCRIPTION OF THE DRAWINGS In the drawings, like reference characters generally refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the exemplary principles of the disclosure. In the following description, various exemplary embodiments of the disclosure are described with reference to the following drawings, in which: FIG. 1 depicts a 3D chip stack including a plurality of chiplets according to an embodiment; FIG. 2 depicts another 3D chip stack including a plurality of chiplets according to an embodiment; FIG. 3 depicts a flow diagram illustrating a method of manufacturing an electrically conductive connection formed on a side surface of one or more chiplets of a chiplet stack including a plurality of chiplets; FIGS. 4A to 4E depict a method of manufacturing a device according to an embodiment; and FIG. 5 depicts a device according to an embodiment. DESCRIPTION The following detailed description refers to the accompanying drawings that show, by way of illustration, exemplary details and embodiments in which aspects of the present disclosure may be practiced. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration”. Any embodiment or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Throughout the drawings, it should be noted that like reference numbers are used to depict the same or similar elements, features, and structures, unless otherwise noted. The phrase “at least one” and “one or more” may be understood to include a numerical quantity greater than or equal to one (e.g., one, two, three, four, [. . . ], etc.). The phrase “at least one of” with regard to a group of elements may be used herein to mean at least one element from the group consisting of the elements. For example, the phrase “at least one of” with regard to a group of elements may be used herein to mean a selection of: one of the listed elements, a plurality of one of the listed elements, a plurality of individual listed elements, or a plurality of a multiple of individual listed elements. The words “plural” and “multiple” in the description and in the claims expressly refer to a quantity greater than one. Accordingly, any phrases explicitly invoking the aforementioned words (e.g., “plural [elements]”, “multiple [elements]”) referring to a quantity of elements expressly refers to more than one of the said elements. For instance, the phrase “a plurality” may be understood to include a numerical quantity greater than or equal to two (e.g., two, three, four, five, [. . . ], etc.). The phrases “group (of)”, “set (of)”, “collection (of)”, “series (of)”, “sequence (of)”, “grouping (of)”, etc., in the description and in the claims, if any, refer to a quantity equal to or greater than one, i.e., one or more. The terms “proper subset”, “reduced subset”, and “lesser subset” refer to a subset of a set that is not equal to the set, illustratively, referring to a subset of a set that contains less elements than the set. The term “data” as used herein may be understood to include information in any suitable analog or digital form, e.g., provided as a file, a portion of a file, a set of files, a signal or stream, a portion of a signal or stream, a set of signals or streams, and the like. Further, the term “data” may also be used to mean a reference to information, e.g., in form of a pointer. The term “data”, however, is not limited to the aforementioned examples and may take various forms and represent any information as understood in the art. The terms “processor” or “controller” as, for example, used herein may be understood as any kind of technological entity that allows handling of data. The data may be handled according to one or more specific functions executed by the processor or controller. Further, a processor or controller as used herein may be understood as any kind of circuit, e.g., any kind of analog or digital circuit. A processor or a controller may thus be or include an analog circuit, digital circuit, mixed-signal circuit, logic circuit, processor, microprocessor, Central Processing Unit (CPU), Graphics Processing Unit (GPU), Digital Signal Processor (DSP), Field Programmable Gate Array (FPGA), int