US-20260130263-A1 - Semiconductor Device and Method of Forming Dummy Vias in WLP

US20260130263A1US 20260130263 A1US20260130263 A1US 20260130263A1US-20260130263-A1

Abstract

A semiconductor device has a semiconductor substrate and first insulating layer formed over the surface of the semiconductor substrate. A dummy via is formed through the first insulating layer. A second insulating layer is formed over the first insulating layer to fill the dummy via. A first conductive layer is formed over the second insulating layer. A bump is formed over the first conductive layer adjacent to the dummy via filled with the second insulating layer. A second conductive layer is formed over a surface of the semiconductor substrate. The dummy via filled with the second insulating layer relieves stress on the second conductive layer. A plurality of dummy vias filled with the second insulating layer can be formed within a designated via formation area. A plurality of dummy vias filled with the second insulating layer can be formed in a pattern.

Inventors

Peik Eng Ooi
Lee Sun Lim

Assignees

STATS ChipPAC Pte. Ltd.

Dates

Publication Date: 20260507
Application Date: 20260105

Claims (20)

1 . A semiconductor device, comprising: a substrate; a first insulating layer formed over a surface of the substrate; a dummy via formed through the first insulating layer and extending to the surface of the substrate; a second insulating layer formed over the first insulating layer and into the dummy via; and a first conductive layer formed over the second insulating layer.
2 . The semiconductor device of claim 1 , further including a second conductive layer formed over the surface of the substrate, wherein the first insulating layer is formed over the second conductive layer.
3 . The semiconductor device of claim 2 , wherein the second insulating layer within the dummy via relieves stress on the second conductive layer.
4 . The semiconductor device of claim 1 , further including a bump formed over the first conductive layer.
5 . The semiconductor device of claim 1 , further including a plurality of dummy vias formed through the first insulating layer within a designated via formation area, wherein the second insulating layer is formed within the dummy vias.
6 . The semiconductor device of claim 1 , further including a plurality of dummy vias formed through the first insulating layer in a pattern, wherein the second insulating layer is formed within the dummy vias.
7 . A semiconductor device, comprising: a substrate; a first insulating layer formed over the surface of the substrate; a dummy via formed through the first insulating layer and extending to the surface of the substrate; and a second insulating layer formed over the first insulating layer and into the dummy via.
8 . The semiconductor device of claim 7 , further including: a first conductive layer formed over the surface of the substrate, wherein the first insulating layer is formed over the first conductive layer; and a second conductive layer formed over the second insulating layer and electrically connected to the first conductive layer.
9 . The semiconductor device of claim 8 , further including a bump formed over the second conductive layer.
10 . The semiconductor device of claim 8 , wherein the second insulating layer within the dummy via relieves stress on the first conductive layer.
11 . The semiconductor device of claim 7 , further including a cutout formed in the first conductive layer.
12 . The semiconductor device of claim 7 , further including a plurality of dummy vias formed through the first insulating layer within a designated via formation area, wherein the second insulating layer is formed within the dummy vias.
13 . The semiconductor device of claim 7 , further including a plurality of dummy vias formed through the first insulating layer in a pattern, wherein the second insulating layer is formed within the dummy vias.
14 . A method of making a semiconductor device, comprising: providing a substrate; forming a first insulating layer over a surface of the substrate; forming a dummy via through the first insulating layer and extending to the surface of the substrate; forming a second insulating layer over the first insulating layer and into the dummy via; and forming a first conductive layer over the second insulating layer.
15 . The method of claim 14 , further including: forming a second conductive layer over the surface of the substrate; and forming the first insulating layer over the second conductive layer.
16 . The method of claim 15 , wherein the second insulating layer within the dummy via relieves stress on the second conductive layer.
17 . The method of claim 14 , further including forming a bump over the first conductive layer.
18 . The method of claim 14 , further including: forming a plurality of dummy vias through the first insulating layer within a designated via formation area; and forming the second insulating layer within the dummy vias.
19 . The method of claim 14 , further including: forming a plurality of dummy vias through the first insulating layer in a pattern; and forming the second insulating layer within the dummy vias.
20 . A method of making a semiconductor device, comprising: providing a substrate; forming a first insulating layer over the surface of the substrate; forming a dummy via through the first insulating layer and extending to the surface of the substrate; and forming a second insulating layer over the first insulating layer and into the dummy via.

Description

CLAIM OF DOMESTIC PRIORITY The present application is a continuation of U.S. Ser. No. 17/819,738 , filed Aug. 15, 2022, which application is incorporated herein. FIELD OF THE INVENTION The present invention relates in general to semiconductor devices and, more particularly, to a semiconductor device and method of forming dummy vias between or adjacent to bumps in a wafer level package (WLP). BACKGROUND OF THE INVENTION Semiconductor devices are commonly found in modern electrical products. Semiconductor devices perform a wide range of functions, such as signal processing, high-speed calculations, transmitting and receiving electromagnetic signals, controlling electrical devices, photo-electric, and creating visual images for television displays. Semiconductor devices are found in the fields of communications, power conversion, networks, computers, entertainment, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment. A semiconductor wafer can have digital and analog circuits formed on or within an active surface of the wafer. A plurality of conductive layers and insulating layers is formed over the semiconductor wafer to provide electrical interconnect for the circuits formed on or within the active surface. The conductive layers include power supply layers and electrical interconnect layers to signal transmission. The conductive layers can experience stress, particularly in areas of high metal concentration, leading to interlayer delamination due to interface locking between similar layers. The stress and delamination is more prominent for multi-layer RDL designs. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1a-1c illustrate a semiconductor wafer with a plurality of semiconductor die separated by a saw street; FIGS. 2a-2f illustrate forming a dummy via between or adjacent to bumps; FIGS. 3a-3d illustrate a process of forming a plurality of dummy vias or adjacent to bumps; FIG. 4 illustrates an alternate pattern of the dummy vias between or adjacent to bumps; FIG. 5 illustrates another pattern of the dummy vias between or adjacent to bumps; and FIG. 6 illustrates a printed circuit board (PCB) with different types of packages disposed on a surface of the PCB. DETAILED DESCRIPTION OF THE DRAWINGS The present invention is described in one or more embodiments in the following description with reference to the figures, in which like numerals represent the same or similar elements. While the invention is described in terms of the best mode for achieving the invention's objectives, it will be appreciated by those skilled in the art that it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents as supported by the following disclosure and drawings. The term “semiconductor die” as used herein refers to both the singular and plural form of the words, and accordingly, can refer to both a single semiconductor device and multiple semiconductor devices. Semiconductor devices are generally manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components, which are electrically connected to form functional electrical circuits. Active electrical components, such as transistors and diodes, have the ability to control the flow of electrical current. Passive electrical components, such as capacitors, inductors, and resistors, create a relationship between voltage and current necessary to perform electrical circuit functions. Back-end manufacturing refers to cutting or singulating the finished wafer into the individual semiconductor die and packaging the semiconductor die for structural support, electrical interconnect, and environmental isolation. To singulate the semiconductor die, the wafer is scored and broken along non-functional regions of the wafer called saw streets or scribes. The wafer is singulated using a laser cutting tool or saw blade. After singulation, the individual semiconductor die are disposed on a package substrate that includes pins or contact pads for interconnection with other system components. Contact pads formed over the semiconductor die are then connected to contact pads within the package. The electrical connections can be made with conductive layers, bumps, stud bumps, conductive paste, or wirebonds. An encapsulant or other molding material is deposited over the package to provide physical support and electrical isolation. The finished package is then inserted into an electrical system, and the functionality of the semiconductor device is made available to the other system components. FIG. 1a shows a semiconductor wafer 100 with a base substrate material 10