US-20260130264-A1 - ENCAPSULATION WARPAGE REDUCTION FOR SEMICONDUCTOR DIE ASSEMBLIES AND ASSOCIATED METHODS AND SYSTEMS

US20260130264A1US 20260130264 A1US20260130264 A1US 20260130264A1US-20260130264-A1

Abstract

Encapsulation warpage reduction for semiconductor die assemblies, and associated methods and systems are disclosed. In one embodiment, a semiconductor die assembly includes an interface die, a stack of semiconductor dies attached to a surface of the interface die, where the stack of semiconductor dies has a first height from the surface. The semiconductor die assembly also includes an encapsulant over the surface and surrounding the stack of semiconductor dies, where the encapsulant includes a sidewall with a first portion extending from the surface to a second height less than the first height and a second portion extending from the second height to the first height. Further, the first portion has a first texture and the second portion has a second texture different from the first texture.

Inventors

Brandon P. Wirz
Liang Chun Chen

Assignees

MICRON TECHNOLOGY, INC.

Dates

Publication Date: 20260507
Application Date: 20251218

Claims (18)

1 . A semiconductor die assembly, comprising: an interface die; a semiconductor die attached to a surface of the interface die, the semiconductor die having a first height from the surface; and an encapsulant over the surface and surrounding the semiconductor die, the encapsulant including an outer sidewall having: a lower segment in a first plane extending from the surface to a second height less than the first height, the lower segment having a first surface texture; and an upper segment in a second plane different from and parallel to the first plane and extending from the second height to the first height, the upper segment having a second surface texture different from the first surface texture, wherein the second plane is spaced closer to a center of the semiconductor die assembly than the first plane.
2 . The semiconductor die assembly of claim 1 , wherein the outer sidewall is a first outer sidewall of the encapsulant, the encapsulant further comprising: a second outer sidewall extending from the surface to the first height, the second outer sidewall having the first surface texture.
3 . The semiconductor die assembly of claim 1 , wherein: the first surface texture is formed by one or more singulation process steps utilized to singulate the interface die; and the second surface texture is formed by contact between a mold frame and the encapsulant.
4 . The semiconductor die assembly of claim 1 , wherein the second surface texture is generally smoother than the first surface texture.
5 . The semiconductor die assembly of claim 1 , wherein the lower segment is aligned with an edge of the interface die.
6 . The semiconductor die assembly of claim 1 , wherein: the interface die corresponds to a logic die or an interposer die; and the semiconductor die corresponds to a memory die.
7 . A semiconductor die assembly, comprising: an interposer; a vertical stack of semiconductor dies attached to a surface of the interposer, the stack having a first height from the surface; and an encapsulant over the surface and surrounding the stack, the encapsulant including an outer sidewall having: a lower segment in a first plane extending from the surface to a second height less than the first height, the lower segment having a first surface texture; and an upper segment in a second plane different from and parallel to the first plane and extending from the second height to the first height, the upper segment having a second surface texture different from the first surface texture, wherein the second plane is spaced closer to a center of the semiconductor die assembly than the first plane.
8 . The semiconductor die assembly of claim 7 , wherein the outer sidewall is a first outer sidewall of the encapsulant, the encapsulant further comprising: a second outer sidewall extending from the surface to the first height, the second outer sidewall having the first surface texture.
9 . The semiconductor die assembly of claim 7 , wherein: the first surface texture is formed by one or more singulation process steps utilized to singulate the interposer; and the second surface texture is formed by contact between a mold frame and the encapsulant.
10 . The semiconductor die assembly of claim 7 , wherein the second surface texture is generally smoother than the first surface texture.
11 . The semiconductor die assembly of claim 7 , wherein the lower segment is aligned with an edge of the interposer.
12 . The semiconductor die assembly of claim 7 , wherein the stack of semiconductor dies includes one or more memory dies.
13 . A semiconductor die assembly, comprising: an interface die; one or more semiconductor dies attached to a surface of the interface die; and an encapsulant over the surface and surrounding the one or more semiconductor dies, the encapsulant including an outer sidewall having: a lower segment in a first plane extending from the surface partway to an upper surface of the semiconductor die assembly, the lower segment having a first surface texture; and an upper segment in a second plane different from and parallel to the first plane and extending from to the upper surface of the semiconductor die assembly, the upper segment having a second surface texture different from the first surface texture, wherein the second plane is spaced closer to a center of the semiconductor die assembly than the first plane.
14 . The semiconductor die assembly of claim 13 , wherein the outer sidewall is a first outer sidewall of the encapsulant, the encapsulant further comprising: a second outer sidewall extending from the surface to the first height, the second outer sidewall having the first surface texture.
15 . The semiconductor die assembly of claim 13 , wherein: the first surface texture is formed by one or more singulation process steps utilized to singulate the interface die; and the second surface texture is formed by contact between a mold frame and the encapsulant.
16 . The semiconductor die assembly of claim 13 , wherein the second surface texture is generally smoother than the first surface texture.
17 . The semiconductor die assembly of claim 13 , wherein the lower segment is aligned with an edge of the interface die.
18 . The semiconductor die assembly of claim 13 , wherein: the interface die corresponds to a logic die or an interposer die; and the one or more semiconductor dies include at least one a memory die.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of U.S. Application No. 18/620,993, filed March 28, 2024, now U.S. Patent No. 12,512,332, which is a divisional of U.S. Patent Application No. 17/315,588, filed May 10, 2021, now U.S. Patent No. 11,955,345, which claims priority to U.S. Provisional Patent Application No. 63/184,899, filed May 6, 2021, now expired; the disclosures of which are incorporated herein by reference in their entireties. TECHNICAL FIELD The present disclosure generally relates to semiconductor die assemblies, and more particularly relates to reducing encapsulation warpage for semiconductor die assemblies and associated methods and systems. BACKGROUND Semiconductor packages typically include a semiconductor die (e.g., memory chip, microprocessor chip, imager chip) mounted on a substrate and encased in a protective covering (e.g., an encapsulating material). The semiconductor die may include functional features, such as memory cells, processor circuits, or imager devices, as well as bond pads electrically connected to the functional features. The bond pads can be electrically connected to corresponding conductive structures of the substrate, which may be coupled to terminals outside the protective covering such that the semiconductor die can be connected to higher level circuitry. Market pressures continually drive semiconductor manufacturers to reduce the size of semiconductor packages to fit within the space constraints of electronic devices. In some semiconductor packages, direct chip attach methods (e.g., flip-chip bonding between the semiconductor die and the substrate) may be used to reduce the footprint of the semiconductor packages. Such direct chip attach methods include directly connecting multiple conductive pillars electrically coupled to the semiconductor die to corresponding conductive structures (e.g., conductive bumps) of the substrate. In this regard, a solder structure may be formed over individual conductive pillars for bonding the conductive pillars to the corresponding conductive structures - e.g., forming interconnects (which may be referred to as joints) that include the conductive pillar, the solder structure, and the conductive bump. Further, an encapsulating material can be applied to protect the semiconductor die. BRIEF DESCRIPTION OF THE DRAWINGS Many aspects of the present technology can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale. Instead, emphasis is placed on illustrating clearly the principles of the present technology. FIG. 1 is a diagram of an interface wafer with stacks of semiconductor dies. FIGS. 2A through 2E illustrate stages of a process for forming semiconductor die assemblies. FIGS. 3A through 3F illustrate stages of a process for forming semiconductor die assemblies in accordance with embodiments of the present technology. FIG. 4 illustrates a stage of a process for forming semiconductor die assemblies in accordance with embodiments of the present technology. FIGS. 5A and 5B illustrate example mold frames in accordance with embodiments of the present technology. FIGS. 5C and 5D illustrate example semiconductor die assemblies in accordance with embodiments of the present technology. FIG. 6 is a semiconductor die assembly in accordance with embodiments of the present technology. FIG. 7 is a block diagram schematically illustrating a system including a semiconductor die assembly configured in accordance with embodiments of the present technology. FIG. 8 is a flowchart of a method of forming a semiconductor die assembly in accordance with embodiments of the present technology. DETAILED DESCRIPTION Specific details of several embodiments directed to reducing wafer warpage for semiconductor die assemblies, and associated systems and methods are described below. Wafer level packaging (WLP) can provide scaled form factors for semiconductor die assemblies (semiconductor device assemblies). The WLP techniques utilizes an interface wafer, to which semiconductor dies or stacks of semiconductor dies (e.g., active dies, known good dies, memory dies) are attached. Individual semiconductor dies (or stacks of semiconductor dies) are aligned with and electrically connected to corresponding interface dies of the interface wafer. The interface dies may include different types of semiconductor dies than the semiconductor dies (e.g., logic dies that control the semiconductor dies) or interposer dies with redistribution layers (RDLs) configured to route electrical signals between the semiconductor dies (or the semiconductor dies of the stacks) and higher level circuitry. For certain semiconductor die assemblies, sizes of individual logic dies and/or interposer dies are greater than areas occupied by corresponding semiconductor dies (or stacks of semiconductor dies) such that additional terminals (e.g., balls in a ball-grid-array (BGA) that are located outside the