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US-20260130267-A1 - SEMICONDUCTOR PACKAGE WITH STIFFENER STRUCTURE AND METHOD OF MANUFACTURING THE SAME

US20260130267A1US 20260130267 A1US20260130267 A1US 20260130267A1US-20260130267-A1

Abstract

A semiconductor package includes a first component, a second component, and a stiffener rib. The first component is disposed on a substrate. The second component is disposed aside the first component and on the substrate. The stiffener rib is disposed between the first component and the second component. The lid is attached to the stiffener rib, the first component and the second component. The lid includes a recess portion on the stiffener rib. A first sidewall and a second sidewall of the recess portion laterally surround the stiffener rib. A first top space between a first top sidewall of the stiffener rib and the first sidewall of the recess portion is greater than a second top space between a second top sidewall of the stiffener rib and the second sidewall of the recess portion.

Inventors

  • Wensen Hung
  • Yu-Ling Tsai
  • Chien-Chia Chiu
  • Tsung-Yu Chen

Assignees

  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date
20260507
Application Date
20260105

Claims (20)

  1. 1 . A semiconductor package, comprising: a first component; a plurality of second components, disposed aside the first component; a stiffener structure, disposed aside the first component and the plurality of second components, the stiffener structure comprising: a stiffener rib between the first component and the plurality of second components, wherein the stiffener rib comprises a first portion and a second portion on the first portion, and a width of the second portion is greater than a width of the first portion; and a lid, attached to the stiffener structure, the first component and the plurality of second components, wherein a plurality of sidewalls of the second portion of the stiffener rib are laterally surrounded by the lid.
  2. 2 . The semiconductor package of claim 1 , wherein the first component has a pair of short sides and a pair of long sides, and the plurality of second components is arranged on opposite sides of the long sides of the first component.
  3. 3 . The semiconductor package of claim 2 , wherein the stiffener rib extends along the pair of long sides of the first component.
  4. 4 . The semiconductor package of claim 1 , further comprising a passive component disposed aside the first portion of the stiffener rib and under the second portion of the stiffener rib.
  5. 5 . The semiconductor package of claim 1 , wherein a thickness of the lid over the stiffener rib is less than a thickness of the lid over the first component.
  6. 6 . The semiconductor package of claim 1 , wherein a thickness of the lid over the stiffener rib is less than a thickness of the lid over the plurality of second components.
  7. 7 . The semiconductor package of claim 6 , wherein a thickness of the first portion of the stiffener rib is equal to or greater than the thickness of the first component or the thickness of the plurality of second components.
  8. 8 . The semiconductor package of claim 1 , wherein the second portion of the stiffener rib is in a stepped shape, and the stiffener rib is adhered to the lid through an adhesive.
  9. 9 . The semiconductor package of claim 1 , wherein the stiffener rib further comprises a third portion, the third portion is in a fillet shape and is at both sides of an intersection formed by the first portion and the second portion.
  10. 10 . The semiconductor package of claim 1 , wherein a bottom surface of the lid on the first component is lower than a top surface of the second portion of the stiffener rib.
  11. 11 . The semiconductor package of claim 1 , wherein the stiffener structure further comprises: a stiffener ring surrounding the first component and the plurality of second components.
  12. 12 . A semiconductor package, comprising: a first component and a plurality of second components, disposed on and electrically connected to a substrate; a stiffener structure, adhered to the substrate, the stiffener structure comprising: a pair of stiffener ribs, wherein each of pair of stiffener ribs comprises a bottom part and a top part on the bottom part, and a width of the top part is greater than a width of the bottom part; and a lid, attached to the first component, the plurality of second components and the stiffener structure, and comprising: a first portion attached to the first component; and a plurality of second portions attached to the plurality of second components, wherein sidewalls of the first portion and the plurality of second portions laterally surround the top parts of the pair of stiffener ribs.
  13. 13 . The semiconductor package of claim 12 , wherein the stiffener structure further comprises an extension portion extending from an edge of the pair of stiffener ribs and extending towards a central region of the semiconductor package.
  14. 14 . The semiconductor package of claim 12 , wherein the stiffener structure further comprises an extension portion extending from an edge of the pair of the stiffener ribs and extending outwards both sides of the pair of stiffener ribs.
  15. 15 . The semiconductor package of claim 12 , wherein the stiffener structure further comprises an extension portion extending from an edge of the pair of the stiffener ribs and the extension portion is in a fillet shape.
  16. 16 . The semiconductor package of claim 12 , wherein the stiffener structure further comprises: a stiffener ring extending along a perimeter of the substrate and surrounding the first component and the plurality of second components, and connected to the pair of stiffener ribs.
  17. 17 . The semiconductor package of claim 16 , wherein the stiffener structure further comprises an extension portion extending from an edge of the pair of stiffener ribs and connecting the two of the pair of the stiffener ribs by extending along a side of the stiffener ring.
  18. 18 . A method of manufacturing a semiconductor package, comprising: bonding a first component and a plurality of second components on a substrate; adhering a stiffener structure on the substrate, the stiffener structure comprising: a pair of stiffener ribs, wherein each of pair of stiffener ribs comprises a bottom part and a top part on the bottom part, and a width of the top part is greater than a width of the bottom part; and attaching a lid to the stiffener structure, the first component and the plurality of second components, wherein the lid comprises: a first portion attached to the first component; and a plurality of second portions attached to the plurality of second components, wherein sidewalls of the first portion and the plurality of second portions laterally surround the top parts of the pair of stiffener ribs.
  19. 19 . The method of claim 18 , wherein the lid is attached to the first component through a first thermal interface material (TIM), the lid is attached to the plurality of second components through a second thermal interface material, and the lid is attached to the pair of stiffener ribs through an adhesive, wherein the adhesive is higher than the first thermal interface material and the second thermal interface material.
  20. 20 . The method of claim 18 , wherein a first bottom space between a first sidewall of the bottom part and a first sidewall of the first component is different from a second bottom space between a second sidewall of the bottom part and a second sidewall of one of the plurality of second components.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is a continuation application of and claims the priority benefit of a prior application Ser. No. 18/789,496, filed on Jul. 30, 2024. The prior application Ser. No. 18/789,496 is a continuation application of and claims the priority benefit of a prior application Ser. No. 18/336,960, filed on Jun. 17, 2023. The prior application Ser. No. 18/336,960 is a continuation application of and claims the priority benefit of a prior application Ser. No. 17/314,002, filed on May 6, 2021, now patented. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification. BACKGROUND In packaging of semiconductor devices, after individual semiconductor dies are manufactured and packaged, the packaged semiconductor dies may be mounted on a packaging substrate with other electronic components, such as other semiconductor dies, to form a semiconductor device. A lid is then attached to the semiconductor device for dissipating the heat generated during the operation; such attachment is through a thermal interface material (TIM) and/or an adhesive. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 is a schematic top view of a semiconductor package with a stiffener structure in accordance with some embodiments of the present disclosure. FIGS. 2A through 2D are respectively schematic cross-sectional views of semiconductor packages with various stiffener ribs along line A-A′ shown in FIG. 1 in accordance with some embodiments of the present disclosure. FIG. 3 is a schematic top view of another semiconductor package with a stiffener structure in accordance with some embodiments of the present disclosure. FIG. 4 is a schematic cross-sectional view of another semiconductor package with a stiffener structure along line B-B′ shown in FIG. 3 in accordance with some embodiments of the present disclosure. FIGS. 5 through 7 are respectively schematic top views of various semiconductor packages with various stiffener structures in accordance with some embodiments of the present disclosure. FIGS. 8 through 12 are a series of respectively schematic cross-sectional views illustrating a method of forming a semiconductor package in accordance with some embodiments of the present disclosure. FIG. 13 provides a flow diagram for a method of forming a semiconductor package in accordance with some embodiments of the present disclosure. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. In semiconductor industry, various chip packages and/or electronic components may be mounted on a packaging circuit substrate to form a semiconductor device. A lid may be attached to the semiconductor device through a thermal interface material (TIM) and/or an adhesive. Usually, the semiconductor devices and the lid are formed of different materials having mismatched coefficient of thermal expansion (CTE). As a result, the semiconductor device and the lid experience significantly different dimensional change under temperature change which may lead to the delaminat