US-20260130268-A1 - ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF

Abstract

An electronic package and a manufacturing method thereof are provided, in which an encapsulating layer embedded with at least one electronic component is provided, then a wiring structure and a circuit structure are sequentially formed on the encapsulating layer, and at least one reinforced blind via is formed in the circuit structure to disperse the stresses in the wiring structure and the circuit structure, thereby preventing the problem of cracking from occurring to the wiring structure or the circuit structure.

Inventors

• Hsing-Yu Liu
• Chih-Sheng Lin
• Chih-Yuan Shih

Assignees

• SILICONWARE PRECISION INDUSTRIES CO., LTD.

Dates

Publication Date

20260507

Application Date

20241230

Priority Date

20241105

Claims (20)

1. 1 . An electronic package, comprising: an encapsulating layer; at least one electronic component embedded in the encapsulating layer; a wiring structure formed on the encapsulating layer and including an insulating layer formed on the encapsulating layer, a wiring layer formed on the insulating layer, and a plurality of first conductive blind vias formed in the insulating layer, wherein the plurality of first conductive blind vias are electrically connected to the wiring layer and the at least one electronic component; a circuit structure formed on the wiring structure and including at least one dielectric layer formed on the insulating layer, at least one circuit layer formed on the dielectric layer, and a plurality of second conductive blind vias formed in the dielectric layer, wherein the plurality of second conductive blind vias are electrically connected to the circuit layer and the wiring layer, wherein the first conductive blind vias and the second conductive blind vias are offset from each other, and a target area is formed in the dielectric layer between the first conductive blind vias and the second conductive blind vias; and a reinforced blind via formed in the target area of the dielectric layer.
2. 2 . The electronic package of claim 1 , wherein the wiring structure and the circuit structure are of redistribution layer specifications.
3. 3 . The electronic package of claim 1 , wherein the circuit structure includes a plurality of the dielectric layers.
4. 4 . The electronic package of claim 3 , wherein a plurality of the reinforced blind vias are arranged in the different dielectric layers.
5. 5 . The electronic package of claim 1 , wherein a plurality of the reinforced blind vias are arranged in the single dielectric layer.
6. 6 . The electronic package of claim 1 , wherein the reinforced blind via is located in a vertical projection area of the electronic component.
7. 7 . The electronic package of claim 1 , wherein the reinforced blind via is located in the dielectric layer adjacent to the insulating layer.
8. 8 . The electronic package of claim 1 , wherein the reinforced blind via, the first conductive blind vias and the second conductive blind vias are offset from each other.
9. 9 . The electronic package of claim 1 , wherein a planar shape of the reinforced blind via is a geometric figure.
10. 10 . The electronic package of claim 1 , wherein a width of the reinforced blind via is less than or equal to a width of the circuit layer.
11. 11 . A method of manufacturing an electronic package, comprising: forming an encapsulating layer on at least one electronic component to encapsulate the at least one electronic component; forming a wiring structure on the encapsulating layer, wherein the wiring structure includes an insulating layer formed on the encapsulating layer, a wiring layer formed on the insulating layer, and a plurality of first conductive blind vias formed in the insulating layer, wherein the plurality of first conductive blind vias are electrically connected to the wiring layer and the at least one electronic component; forming a circuit structure on the wiring structure, wherein the circuit structure includes at least one dielectric layer formed on the insulating layer, at least one circuit layer formed on the dielectric layer, and a plurality of second conductive blind vias formed in the dielectric layer, wherein the plurality of second conductive blind vias are electrically connected to the circuit layer and the wiring layer, wherein the first conductive blind vias and the second conductive blind vias are offset from each other, and a target area is formed in the dielectric layer between the first conductive blind vias and the second conductive blind vias; and forming a reinforced blind via in the target area of the dielectric layer.
12. 12 . The method of claim 11 , wherein the wiring structure and the circuit structure are of redistribution layer specifications.
13. 13 . The method of claim 11 , wherein the circuit structure includes a plurality of the dielectric layers.
14. 14 . The method of claim 13 , wherein a plurality of the reinforced blind vias are arranged in the different dielectric layers.
15. 15 . The method of claim 11 , wherein a plurality of the reinforced blind vias are arranged in the single dielectric layer.
16. 16 . The method of claim 11 , wherein the reinforced blind via is located in a vertical projection area of the electronic component.
17. 17 . The method of claim 11 , wherein the reinforced blind via is located in the dielectric layer adjacent to the insulating layer.
18. 18 . The method of claim 11 , wherein the reinforced blind via, the first conductive blind vias and the second conductive blind vias are offset from each other.
19. 19 . The method of claim 11 , wherein a planar shape of the reinforced blind via is a geometric figure.
20. 20 . The method of claim 11 , wherein a width of the reinforced blind via is less than or equal to a width of the circuit layer.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS The present application is based upon and claims the right of priority to TW Patent Application No. 113142364, filed Nov. 5, 2024, the disclosure of which is hereby incorporated by reference herein in its entirety for all purposes BACKGROUND 1. Technical Field The present disclosure relates to a semiconductor packaging technology, and more particularly, to an electronic package that can improve reliability and a manufacturing method thereof. 2. Description of Related Art In order to ensure the continued miniaturization and multi-functionality of electronic products and communication equipment, semiconductor packages need to develop towards miniaturization in order to facilitate the connection of multiple pins. For example, packaging types including flip-chip packaging processes, fan-out wiring and embedded component processes, etc., are commonly used in advanced packaging processes. FIG. 1A to FIG. 1C are schematic cross-sectional views illustrating a manufacturing method of a conventional semiconductor package 1. As shown in FIG. 1A, a plurality of semiconductor chips 12 are disposed on a carrier 9, and then the semiconductor chips 12 are encapsulated by an encapsulant 13. As shown in FIG. 1B, a build-up structure 15 is formed on the encapsulant 13, and a plurality of solder bumps 16 are formed on the build-up structure 15, wherein the build-up structure 15 includes a dielectric layer 150 formed on the encapsulant 13, a circuit layer 151 formed on the dielectric layer 150, and a plurality of conductive blind holes 152 formed in the dielectric layer 150. The conductive blind holes 152 are electrically connected to the circuit layer 151 and the semiconductor chips 12. As shown in FIG. 1C, the carrier 9 is removed, and a singulation process is performed along a cutting path S shown in FIG. 1B. However, in the manufacturing method of the conventional semiconductor package 1, the semiconductor chips 12 are first embedded in the encapsulant 13, and then the build-up structure 15 is formed. Therefore, no underfill is used as a stress buffer mechanism between the build-up structure 15 and the semiconductor chips 12, and the build-up structure 15 is prone to stress concentration problems in subsequent processes so that the build-up structure 15 is to be cracked (such as cracks K shown in FIG. 1C), thereby damaging the circuit layer 151. Therefore, there is a need for a solution that addresses the aforementioned shortcomings in the prior art. SUMMARY In view of the aforementioned shortcomings of the prior art, the present disclosure provides an electronic package, which comprises: an encapsulating layer; at least one electronic component embedded in the encapsulating layer; a wiring structure formed on the encapsulating layer and including an insulating layer formed on the encapsulating layer, a wiring layer formed on the insulating layer, and a plurality of first conductive blind vias formed in the insulating layer, wherein the plurality of first conductive blind vias are electrically connected to the wiring layer and the at least one electronic component; a circuit structure formed on the wiring structure and including at least one dielectric layer formed on the insulating layer, at least one circuit layer formed on the dielectric layer, and a plurality of second conductive blind vias formed in the dielectric layer, wherein the plurality of second conductive blind vias are electrically connected to the circuit layer and the wiring layer, wherein the first conductive blind vias and the second conductive blind vias are offset from each other, and a target area is formed in the dielectric layer between the first conductive blind vias and the second conductive blind vias; and a reinforced blind via formed in the target area of the dielectric layer. The present disclosure also provides a method of manufacturing an electronic package, the method comprises: forming an encapsulating layer on at least one electronic component to encapsulate the at least one electronic component; forming a wiring structure on the encapsulating layer, wherein the wiring structure includes an insulating layer formed on the encapsulating layer, a wiring layer formed on the insulating layer, and a plurality of first conductive blind vias formed in the insulating layer, wherein the plurality of first conductive blind vias are electrically connected to the wiring layer and the at least one electronic component; forming a circuit structure on the wiring structure, wherein the circuit structure includes at least one dielectric layer formed on the insulating layer, at least one circuit layer formed on the dielectric layer, and a plurality of second conductive blind vias formed in the dielectric layer, wherein the plurality of second conductive blind vias are electrically connected to the circuit layer and the wiring layer, wherein the first conductive blind vias and the second conductive blind vias are offset