US-20260130270-A1 - PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

US20260130270A1US 20260130270 A1US20260130270 A1US 20260130270A1US-20260130270-A1

Abstract

A package structure includes a substrate, an interposer module, a chip module, and a first encapsulant. The interposer module is arranged on the substrate. The chip module is arranged on the interposer module. The chip module is electrically connected to the substrate through the interposer module. The first encapsulant encapsulates the chip module and the interposer module and directly contacts the substrate. A bottom surface of the first encapsulant and a top surface of the substrate are coplanar. A manufacturing method of a package structure is also disclosed.

Inventors

Shang-Yu Chang Chien
Yi-Kai FU

Assignees

POWERTECH TECHNOLOGY INC.

Dates

Publication Date: 20260507
Application Date: 20251020
Priority Date: 20241106

Claims (19)

1 . A package structure, comprising: a substrate; an interposer module, disposed on the substrate; a chip module, disposed on the interposer module, wherein the chip module is electrically connected to the substrate through the interposer module; and a first encapsulant, encapsulating the chip module and the interposer module and directly contacting the substrate, and a bottom surface of the first encapsulant is coplanar with a top surface of the substrate.
2 . The package structure as claimed in claim 1 , wherein the first encapsulant exposes a top surface of the chip module.
3 . The package structure as claimed in claim 1 , wherein an outer sidewall of the first encapsulant is between an outer sidewall of the interposer module and an outer sidewall of the substrate.
4 . The package structure as claimed in claim 1 , wherein a thickness of the first encapsulant is equal to a vertical distance from a top surface of the chip module to the top surface of the substrate.
5 . The package structure as claimed in claim 1 , wherein the first encapsulant covers a second encapsulant of a part of the interposer module.
6 . The package structure as claimed in claim 1 , further comprising a plurality of first conductive terminals between the substrate and the interposer module, and a plurality of second conductive terminals between the interposer module and the chip module, wherein the plurality of first conductive terminals and the plurality of second conductive terminals are recessed within the first encapsulant.
7 . The package structure as claimed in claim 6 , wherein the plurality of first conductive terminals and the plurality of second conductive terminals are wrapped by a first protective member and a second protective member, respectively.
8 . The package structure as claimed in claim 7 , wherein a material of the first protective member and a material of the second protective member are respectively selected from a non-conductive film, a capillary underfill material, the first encapsulant or a combination thereof, and the materials of the first protective member and the second protective member are the same or different.
9 . The package structure as claimed in claim 1 , wherein the first encapsulant comprises an overflow portion, causing a curvature to be formed at an interface between an outer sidewall of the first encapsulant and the substrate.
10 . A method of manufacturing a package structure, comprising: providing a substrate; providing an interposer module, wherein the interposer module is in a singulated manner; disposing the interposer module on the substrate; providing a chip module; disposing the chip module on the interposer module, wherein the chip module is electrically connected to the substrate through the interposer module; and forming a first encapsulant to encapsulate the chip module and the interposer module and directly contact the substrate.
11 . The method of manufacturing the package structure as claimed in claim 10 , further comprising executing a planarization process after forming the first encapsulant to expose a top surface of the chip module.
12 . The method of manufacturing the package structure as claimed in claim 10 , wherein a singulation process is not executed after forming the first encapsulant.
13 . The method of manufacturing the package structure as claimed in claim 10 , further comprising: joining the interposer module and the substrate through a plurality of first conductive terminals; joining the chip module and the interposer module through a plurality of second conductive terminals; and wrapping the plurality of first conductive terminals and the plurality of second conductive terminals respectively through a first protective member and a second protective member.
14 . The method of manufacturing the package structure as claimed in claim 13 , wherein the first protective member and the second protective member are respectively formed by executing a dispensing process or a film attaching process.
15 . The method of manufacturing the package structure as claimed in claim 13 , wherein the second protective member is formed before disposing the chip module on the interposer module, or the second protective member is formed after disposing the chip module on the interposer module.
16 . The method of manufacturing the package structure as claimed in claim 13 , wherein the first protective member and/or the second protective member is a part of the first encapsulant.
17 . The method of manufacturing the package structure as claimed in claim 10 , wherein the step of forming the interposer module comprises: disposing a plurality of bridge chips on a carrier; forming a second encapsulant to encapsulate the plurality of bridge chips; removing the carrier; and executing a singulation process.
18 . The method of manufacturing the package structure as claimed in claim 11 , wherein the first encapsulant exposes a partial area on the substrate.
19 . The method of manufacturing the package structure as claimed in claim 10 , wherein the interposer module is disposed on the substrate before disposing the chip module on the interposer module.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims the priority benefit of Taiwan application serial no. 113142462, filed on Nov. 6, 2024. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification. BACKGROUND Technical Field The present disclosure relates to a package structure and a manufacturing method thereof. Description of Related Art With the advancement of technology, market demands for electronic products have become increasingly stringent. Consequently, ensuring the superior quality of package structures has emerged as a critical subject of current research and development endeavors. SUMMARY The present disclosure provides a package structure and a manufacturing method thereof, through which the yield may be effectively improved, thereby ensuring good quality of the package structure. A package structure of the present disclosure includes a substrate, an interposer module, a chip module, and a first encapsulant. The interposer module is disposed on the substrate. The chip module is set on the interposer module. The chip module is electrically connected to the substrate through the interposer module. The first encapsulant encapsulates the chip module and the interposer module and directly contacts the substrate. The bottom surface of the first encapsulant is coplanar with the top surface of the substrate. A manufacturing method of a package structure of the present disclosure at least includes: providing a substrate; providing an interposer module in a singulated manner; disposing the interposer module on the substrate; providing a chip module; disposing the chip module on the interposer module, causing the chip module to be electrically connected to the substrate through the interposer module; and forming a first encapsulant to encapsulate the chip module and the interposer module and directly contact the substrate. Based on the above, since the number of manufacturing process steps that the chip module goes through may be reduced, the risk of defect rate in the process may be lowered. At the same time, based on the protection of the encapsulant, the overall structural strength may be improved. Accordingly, the yield of the package structure of the present disclosure may be effectively improved, thereby ensuring good quality of the package structure. To make the above-mentioned features and advantages of the present disclosure more evident and easy to understand, exemplary embodiments are described below with reference to the accompanying drawings in detail as follows. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1G are partial cross-sectional schematic views of a partial manufacturing method of a package structure according to an embodiment of the present disclosure. FIG. 2, FIG. 3, FIG. 4, FIG. 5, FIG. 6, FIG. 7, FIG. 8, FIG. 9, FIG. 10, FIG. 11, FIG. 12, and FIG. 13 are partial cross-sectional schematic views of package structures according to some embodiments of the present disclosure. DESCRIPTION OF THE EMBODIMENTS The directional terms (e.g., upper, lower, right, left, front, back, top, bottom) used in this document are only for reference to the accompanying drawings and are not intended to imply absolute orientation. Unless explicitly stated otherwise, any method described herein may not be construed as requiring its steps to be performed in a specific order. Refer to the drawings of this embodiment to more comprehensively illustrate the present disclosure. However, the present disclosure may also be embodied in various different forms and should not be limited to the embodiments described herein. The thickness, dimensions or size of layers or areas in the drawings may be exaggerated for clarity. The same or similar reference numbers indicate the same or similar components, which will not be described repeatedly in the following paragraphs. It should be understood that although the terms “first”, “second”, “third”, etc. may be used herein to describe various components, parts, areas, layers and/or portions, these components, parts, areas, layers and/or portions should not be limited by these terms. These terms are only used to distinguish one component, part, area, layer or portion from another component, part, area, layer or portion. Unless otherwise stated, the term “between” used in this specification for defining numerical ranges is intended to cover ranges equal to the stated endpoint values as well as ranges between the stated endpoint values. For example, a dimensional range between a first value and a second value means that the dimensional range may cover the first value, the second value, and any value between the first value and the second value. FIG. 1A to FIG. 1G are partial cross-sectional schematic views of a partial manufacturing method of a package structure according to an embodiment of the present disclosure. Referring to FIG. 1A to FIG. 1E, the manufacturing process of the inter