US-20260130271-A1 - SEMICONDUCTOR PACKAGE

US20260130271A1US 20260130271 A1US20260130271 A1US 20260130271A1US-20260130271-A1

Abstract

A semiconductor package includes a first interconnect component, a second interconnect component and a third encapsulant. The first interconnect component includes a first encapsulant. The second interconnect component is laterally spaced apart from the first interconnect component and includes a second encapsulant. The third encapsulant laterally encapsulates the first interconnect component and the second interconnect component. The first encapsulant includes a first filler having a first average size, and the second encapsulant includes a second filler having a second average size different from the first average size.

Inventors

Mao-Yen Chang
Hsiu-Jen Lin
WEI-JIE HUANG
Jeng-An Wang
Hao-Cheng Hou
Tsung-Ding Wang
CHENG-YU KUO
Hsien-Chien Hsieh
Yao-Jen Chang
Ping-Kang Huang

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date: 20260507
Application Date: 20241107

Claims (20)

1 . A semiconductor package, comprising: a first interconnect component comprising a first encapsulant; a second interconnect component laterally spaced apart from the first interconnect component and comprising a second encapsulant; and a third encapsulant laterally encapsulating the first interconnect component and the second interconnect component; wherein the first encapsulant comprises a first filler having a first average size, and the second encapsulant comprises a second filler having a second average size different from the first average size.
2 . The semiconductor package as claimed in claim 1 , wherein the second interconnect component further comprises: an integrated passive device; and a via structure spaced apart from the integrated passive device by a gap, wherein the second encapsulant is in the gap and laterally surrounds the integrated passive device and the via structure.
3 . The semiconductor package as claimed in claim 2 , wherein: a width of the gap is larger than or equal to 20 μm and smaller than or equal to 25 μm, and a depth of the gap is smaller than or equal to 40 μm.
4 . The semiconductor package as claimed in claim 2 , wherein the second interconnect component further comprises: an interconnect structure; and a semiconductor die, wherein the second encapsulant, the integrated passive device and the via structure are disposed on a side of the interconnect structure that is opposite to the semiconductor die.
5 . The semiconductor package as claimed in claim 4 , wherein: the integrated passive device comprises an integrated voltage regulator, and the semiconductor die comprises a logic die or a power management die.
6 . The semiconductor package as claimed in claim 1 , wherein: the first encapsulant comprises a liquid type molding compound, the second encapsulant comprises a lamination type molding compound, and the second average size of the second filler is smaller than the first average size of the first filler.
7 . The semiconductor package as claimed in claim 6 , wherein: the second average size of the second filler is larger than or equal to 1 μm and smaller than or equal to 5 μm, and the first average size of the first filler is larger than 5 μm.
8 . A semiconductor package, comprising: a first interconnect component comprising a first encapsulant; a second interconnect component laterally spaced apart from the first interconnect component and comprising a second encapsulant; and a third encapsulant laterally encapsulating the first interconnect component and the second interconnect component; wherein the first encapsulant has a first average thickness, and the second encapsulant has a second average thickness different from the first average thickness.
9 . The semiconductor package as claimed in claim 8 , wherein the second interconnect component further comprises: an integrated passive device; and a via structure spaced apart from the integrated passive device by a gap, wherein the second encapsulant is in the gap and laterally surrounds the integrated passive device and the via structure.
10 . The semiconductor package as claimed in claim 9 , wherein the second encapsulant in the gap has a first thickness and the second encapsulant over the integrated passive device has a second thickness smaller than the first thickness.
11 . The semiconductor package as claimed in claim 10 , wherein the second thickness is smaller than or equal to 10 μm.
12 . The semiconductor package as claimed in claim 9 , wherein: a width of the gap is larger than or equal to 20 μm and smaller than or equal to 25 μm, and a depth of the gap is smaller than or equal to 40 μm.
13 . The semiconductor package as claimed in claim 9 , wherein the second interconnect component further comprises: an interconnect structure; and a semiconductor die, wherein the second encapsulant, the integrated passive device and the via structure are disposed on a side of the interconnect structure that is opposite to the semiconductor die.
14 . The semiconductor package as claimed in claim 13 , wherein: the integrated passive device comprises an integrated voltage regulator, and the semiconductor die comprises a logic die or a power management die.
15 . The semiconductor package as claimed in claim 8 , wherein: the first encapsulant comprises a liquid type molding compound, the second encapsulant comprises a lamination type molding compound, and the second average thickness of the second encapsulant is smaller than the first average thickness of the first encapsulant.
16 . A semiconductor package, comprising: a first interconnect component comprising a first encapsulant; a second interconnect component laterally spaced apart from the first interconnect component and comprising a second encapsulant and an integrated passive device surrounded by the second encapsulant; a third encapsulant laterally encapsulating the first interconnect component and the second interconnect component; and a redistribution structure disposed on the first interconnect component, the second interconnect component and the third encapsulant, wherein a portion of the second encapsulant is located between the integrated passive device and the redistribution structure.
17 . The semiconductor package as claimed in claim 16 , wherein the integrated passive device comprises an integrated voltage regulator.
18 . The semiconductor package as claimed in claim 17 , wherein a thickness of the second encapsulant located between the integrated passive device and the redistribution structure is smaller than or equal to 10 μm.
19 . The semiconductor package as claimed in claim 16 , wherein the second interconnect component further comprises: a via structure spaced apart from the integrated passive device by a gap, wherein the second encapsulant is in the gap and laterally surrounds the integrated passive device and the via structure.
20 . The semiconductor package as claimed in claim 19 , wherein the second encapsulant in the gap has a first thickness and the second encapsulant located between the integrated passive device and the redistribution structure has a second thickness smaller than the first thickness.

Description

BACKGROUND The semiconductor industry has experienced rapid growth due to ongoing improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, improvement in integration density has resulted from iterative reduction of minimum feature size, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices has grown, a need for smaller and more creative packaging techniques of semiconductor dies has emerged. An example of such packaging systems is Package-on-Package (PoP) technology. In a PoP device, a top semiconductor package is stacked on top of a bottom semiconductor package to provide a high level of integration and component density. PoP technology generally enables production of semiconductor devices with enhanced functionalities and small footprints on a printed circuit board (PCB). BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 through FIG. 9 illustrate cross-sectional views of intermediate steps during a process for forming a semiconductor package in accordance with some embodiments of the present disclosure. FIG. 10 is a schematic cross-sectional view of another semiconductor package in accordance with some embodiments of the present disclosure. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Embodiments discussed herein is related to a semiconductor package including two or more interconnect components. The interconnect components may include electrical routing, through vias, integrated devices such as integrated passive devices (IPDs) or local routing structures, or the like. Semiconductor devices may be attached to the two or more interconnect components. In some cases, by using multiple interconnect components in a semiconductor package as described herein, heat dissipation and/or electrical performances of the semiconductor devices may be improved, reliability of at least one of the interconnect components may be improved, and/or the yield may be increased. For example, by integrate an integrated passive device such as an integrated voltage regulator into one of the interconnect components, heat dissipation and/or electrical performances of the semiconductor devices may be improved. Additionally, by changing the method and/or material for forming the encapsulant in the interconnect component including the integrated passive device, voids generated at the interface between the encapsulant and the underlying component/layer due to significant temperature change during the manufacturing process (e.g., a post reflow process or a ball mount process) and/or reliability test process may be reduced, thereby improving reliability and/or increasing yield. Different types of interconnect structures may be used within the same semiconductor package, which can allow for design flexibility and performance improvements. FIG. 1 through FIG. 9 illustrate cross-sectional views of intermediate steps during a process for forming a semiconductor package in accordance with some embodime