US-20260130273-A1 - SEMICONDUCTOR PACKAGE

Abstract

A semiconductor package includes a first semiconductor chip, second semiconductor chips stacked on the first semiconductor chip, a first bonding layer structure between the second semiconductor chips and including a first bonding pad structure, and a filling pattern contacting at least a portion of each of the second semiconductor chips and including silicon oxide or polymer. A sidewall of the filling pattern is aligned with a sidewall of the first semiconductor chip in the vertical direction. The first bonding layer structure includes first and second bonding layers contacting each other. The first bonding pad structure includes first and second bonding pads in the first and second bonding layers, respectively, and contacting each other. The first bonding layer contacts an upper surface of a lower one of the second semiconductor chips. The second bonding layer contacts a lower surface of an upper one of the second semiconductor chips.

Inventors

• Joohee Jang
• Hojin Lee
• Seokho KIM
• Dongchan Lim

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260507

Application Date

20251031

Priority Date

20241104

Claims (20)

1. 1 . A semiconductor package comprising: a first semiconductor chip; a plurality of second semiconductor chips stacked in a vertical direction on the first semiconductor chip; a first bonding layer structure between the plurality of second semiconductor chips, the first bonding layer structure including a first bonding pad structure; and a filling pattern contacting at least a portion of each of the plurality of second semiconductor chips and including silicon oxide or polymer, wherein a sidewall of the filling pattern is aligned with a sidewall of the first semiconductor chip in the vertical direction, wherein the first bonding layer structure includes a first bonding layer and a second bonding layer that are stacked in the vertical direction, the first and second bonding layers contacting each other, wherein the first bonding pad structure includes a first bonding pad in the first bonding layer and a second bonding pad in the second bonding layer, the first and second bonding pads contacting each other, wherein the plurality of second semiconductor chips include at least a first chip and a second chip that is positioned higher than the first chip, wherein the first bonding layer contacts an upper surface of the first chip of the plurality of second semiconductor chips, and wherein the second bonding layer contacts a lower surface of the second chip of the plurality of second semiconductor chips.
2. 2 . The semiconductor package of claim 1 , wherein the filling pattern includes the polymer, wherein the polymer includes at least one of benzocyclobutene, polyimide, or imide-phenol resin.
3. 3 . The semiconductor package of claim 1 , wherein a planar area of the first bonding layer is greater than a planar area of the second bonding layer.
4. 4 . The semiconductor package of claim 1 , wherein the filling pattern contacts a sidewall of the second bonding layer.
5. 5 . The semiconductor package of claim 1 , wherein the filling pattern contacts an upper surface of an edge portion of the first bonding layer.
6. 6 . The semiconductor package of claim 1 , wherein each of the plurality of second semiconductor chips includes: a substrate having first and second surfaces opposite to each other in the vertical direction; a protective pattern structure on the second surface of the substrate and contacting a lower surface of the first bonding layer structure; and a through-electrode structure extending through the substrate and the protective pattern structure.
7. 7 . The semiconductor package of claim 6 , wherein a planar area of the protective pattern structure is greater than a planar area of the substrate.
8. 8 . The semiconductor package of claim 6 , wherein the filling pattern contacts a lower surface of an edge portion of the protective pattern structure.
9. 9 . The semiconductor package of claim 1 , comprising a second bonding layer structure between the first semiconductor chip and the first chip of the plurality of second semiconductor chips, the second bonding layer structure including a second bonding pad structure.
10. 10 . The semiconductor package of claim 9 , wherein the second bonding layer structure includes a third bonding layer and a fourth bonding layer that are stacked in the vertical direction, the third and fourth bonding layers contacting each other, wherein the second bonding pad structure includes a third bonding pad in the third bonding layer and a fourth bonding pad in the fourth bonding layer, the third and fourth bonding pads contacting each other, wherein the third bonding layer contacts an upper surface of the first semiconductor chip, and wherein the fourth bonding layer contacts a lower surface of a lowermost one of the plurality of second semiconductor chips.
11. 11 . The semiconductor package of claim 10 , wherein a planar area of the third bonding layer is greater than a planar area of the fourth bonding layer.
12. 12 . The semiconductor package of claim 1 , further comprising a second bonding layer structure between the first semiconductor chip and the first chip of the plurality of second semiconductor chips, wherein the first semiconductor chip includes: a substrate having first and second surfaces opposite to each other in the vertical direction; a protective pattern structure on the second surface of the substrate and contacting a lower surface of the second bonding layer structure; and a through-electrode structure extending through the substrate and the protective pattern structure.
13. 13 . The semiconductor package of claim 12 , wherein a planar area of the protective pattern structure is equal to a planar area of the substrate.
14. 14 . The semiconductor package of claim 1 , wherein the first bonding layer structure includes silicon carbonitride or silicon oxide, and wherein the first bonding pad structure includes copper.
15. 15 . A semiconductor package comprising: a first semiconductor chip; a bonding layer structure positioned on the first semiconductor chip, the bonding layer structure including a bonding pad structure; a second semiconductor chip positioned on the bonding layer structure, the second semiconductor chip including: a substrate having first and second surfaces opposite to each other in a vertical direction, an insulating interlayer on the first surface of the substrate and contacting an upper surface of the bonding layer structure, a protective pattern structure on the second surface of the substrate, and a through-electrode structure (i) extending through the substrate, the insulating interlayer, and the protective pattern structure and (ii) contacting the bonding pad structure; and a filling pattern that (i) is positioned on the bonding layer structure, (ii) contacts a sidewall of the substrate, a sidewall of the insulating interlayer, and a lower surface of the protective pattern structure, and (iii) includes silicon oxide or polymer.
16. 16 . The semiconductor package according to claim 15 , wherein the filling pattern contacts an upper surface of an edge portion of the bonding layer structure.
17. 17 . The semiconductor package according to claim 15 , wherein a planar area of the protective pattern structure is equal to a planar area of the first semiconductor chip.
18. 18 . A semiconductor package comprising: a buffer die; middle core dies stacked on the buffer die in a vertical direction; a first bonding layer structure between the buffer die and a lowermost one of the middle core dies, the first bonding layer structure including a first bonding pad structure; a second bonding layer structure between the middle core dies, the second bonding layer structure including a second bonding pad structure; a third bonding layer structure on an uppermost one of the middle core dies, the third bonding layer structure including a third bonding pad structure; a top core die positioned on the third bonding layer structure; and a filling pattern contacting a sidewall of a portion of each of the middle core dies, wherein a sidewall of the filling pattern is aligned with a sidewall of the buffer die in the vertical direction, and the filling pattern includes silicon oxide or polymer.
19. 19 . The semiconductor package according to claim 18 , wherein the filling pattern contacts an upper surface of an edge portion of the first bonding layer structure or the second bonding layer structure.
20. 20 . The semiconductor package according to claim 18 , further comprising: a molding member covering the sidewall of the buffer die, a sidewall of a portion of each of the first bonding layer structure, the second bonding layer structure, and the third bonding layer structure, a sidewall of a portion of each of the middle core dies, the sidewall of the filling pattern, and an upper surface of the top core die.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2024-0154394, filed on Nov. 4, 2024, in the Korean Intellectual Property Office (KIPO), the contents of which are herein incorporated by reference in their entirety. BACKGROUND In some examples, a high bandwidth memory (HBM) package may include a plurality of memory chips stacked on a logic chip in a vertical direction, and the memory chips may be bonded with each other by a bonding layer. If the bonding state between the memory chips is good, the HBM package may have enhanced performance, and thus a method of enhancing the bonding state between the memory chips may be desired. SUMMARY Implementations according to present disclosure provides a semiconductor package having enhanced electrical characteristics. An aspect of the present disclosure provides a semiconductor package. The semiconductor package may include a first semiconductor chip, second semiconductor chips stacked in a vertical direction on the first semiconductor chip, a first bonding layer structure between the second semiconductor chips and including a first bonding pad structure, and a filling pattern contacting at least a portion of each of the second semiconductor chips and including silicon oxide or polymer. A sidewall of the filling pattern may be aligned with a sidewall of the first semiconductor chip in the vertical direction. The first bonding layer structure may include a first bonding layer and a second bonding layer stacked in the vertical direction. The first and second bonding layers may contact each other. The first bonding pad structure may include a first bonding pad and a second bonding pad in the first bonding layer and the second bonding layer, respectively. The first and second bonding pads may contact each other. The first bonding layer may contact an upper surface of a lower one of the second semiconductor chips. The second bonding layer may contact a lower surface of an upper one of the second semiconductor chips. Another aspect of the present disclosure provides a semiconductor package. The semiconductor package may include a first semiconductor chip, a bonding layer structure, a second semiconductor chip and a filling pattern. The bonding layer structure may be disposed on the first semiconductor chip and may include a bonding pad structure. The second semiconductor chip may be disposed on the bonding layer structure. The second semiconductor chip may include a substrate having first and second surfaces opposite to each other in a vertical direction, an insulating interlayer on the first surface of the substrate and contacting an upper surface of the bonding layer structure, a protective pattern structure on the second surface of the substrate, and a through electrode structure extending through the substrate, the insulating interlayer and the protective pattern structure and contacting the bonding pad structure. The filling pattern may be disposed on the bonding layer structure and may contact a sidewall of the substrate, a sidewall of the insulating interlayer and a lower surface of the protective pattern structure. The filling pattern may include silicon oxide or polymer. Another aspect of the present disclosure provides a semiconductor package. The semiconductor package may include a buffer die, middle core dies stacked on the buffer die in a vertical direction, a first bonding layer structure between the buffer die and a lowermost one of the middle core dies and including a first bonding pad structure, a second bonding layer structure between the middle core dies and including a second bonding pad structure, a third bonding layer structure on an uppermost one of the middle core dies and including a third bonding pad structure, a top core die on the third bonding layer structure, and a filling pattern contacting a sidewall of a portion of each of the middle core dies, a sidewall of the filling pattern being aligned with a sidewall of the buffer die in the vertical direction and including silicon oxide or polymer. In some implementations, the semiconductor may include the semiconductor chips stacked in the vertical direction, and the semiconductor chips may be bonded with each other through the bonding layer structure including the bonding pad structure. The bonding layer structure may include the bonding layers stacked in the vertical direction, and no void may exist between the bonding layers. Thus, the semiconductor package including the semiconductor chips bonded to each other through the bonding layer structure may have enhanced electrical characteristics. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view illustrating an example of a semiconductor package. FIGS. 2 to 17 are plan views and cross-sectional views illustrating an example of a method of manufacturing a semiconductor package. FIGS. 18 to 20 are cross-sectional views illustrating an example of a method of