US-20260130275-A1 - SEMICONDUCTOR PACKAGE

US20260130275A1US 20260130275 A1US20260130275 A1US 20260130275A1US-20260130275-A1

Abstract

A semiconductor device may include a semiconductor substrate, an element layer on the semiconductor substrate, a wiring layer on the element layer, and a buffer layer provided between the semiconductor substrate and the element layer or between the element layer and the wiring layer. The buffer layer may include a first buffer layer including a plurality of first voids spaced apart from each other and a second buffer layer provided on the first buffer layer. The buffer layer includes: a first buffer layer including a plurality of first voids spaced apart from each other, and a second buffer layer provided on the first buffer layer and including a plurality of second voids spaced apart from each other, The plurality of second voids are disposed at a different height level than the plurality of first voids. The plurality of second voids include a plurality of pairs of adjacent second voids. In a plan view, each of the first voids of the buffer layer is disposed between a corresponding one of the plurality of pairs of adjacent second voids.

Inventors

Jaehyuk Choi

Assignees

SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date: 20260507
Application Date: 20250626
Priority Date: 20241106

Claims (20)

1 . A semiconductor device comprising: a semiconductor substrate; an element layer on the semiconductor substrate; a wiring layer on the element layer; and a buffer layer provided between the semiconductor substrate and the element layer or between the element layer and the wiring layer, wherein the buffer layer includes: a first buffer layer including a plurality of first voids spaced apart from each other, and a second buffer layer provided on the first buffer layer and including a plurality of second voids spaced apart from each other, wherein the plurality of second voids are disposed at a different height level than the plurality of first voids, wherein the plurality of second voids include a plurality of pairs of adjacent second voids, and wherein, in a plan view, each of the first voids of the buffer layer is disposed between a corresponding one of the plurality of pairs of adjacent second voids.
2 . The semiconductor device of claim 1 , wherein the buffer layer further includes: a third buffer layer interposed between the first buffer layer and the second buffer layer, a fourth buffer layer provided on a lower surface of the first buffer layer, and a fifth buffer layer provided on an upper surface of the second buffer layer, and wherein the first voids are vertically spaced apart from the second voids by the third buffer layer.
3 . The semiconductor device of claim 1 , wherein: a width of each of the first voids and the second voids is 3 μm to 10 μm, a distance between two adjacent second voids among the second voids is uniform, and a distance between two adjacent first voids among the first voids is uniform.
4 . The semiconductor device of claim 1 , wherein each of a thickness of the first buffer layer and a thickness of the second buffer layer is 1 μm to 2 μm.
5 . The semiconductor device of claim 1 , wherein the buffer layer is interposed between the semiconductor substrate and the element layer.
6 . The semiconductor device of claim 1 , wherein the element layer includes a capacitor including: a first electrode, a capacitor dielectric layer covering the first electrode, and having a uniform thickness, and a second electrode covering the first electrode on the capacitor dielectric layer.
7 . The semiconductor device of claim 1 , wherein the buffer layer is interposed between the element layer and the wiring layer.
8 . The semiconductor device of claim 7 , wherein: the buffer layer includes a first region and a second region, the first voids and the second voids constitute a buffer pattern of the buffer layer in the first region, the buffer layer further includes a through-via penetrating the buffer layer in the second region, and the through-via electrically connects the element layer and the wiring layer.
9 . The semiconductor device of claim 1 , wherein: an upper surface of the first buffer layer is vertically spaced apart from a lower surface of the second buffer layer, and a separation distance between the lower surface of the second buffer layer and the upper surface of the first buffer layer is 1 μm to 2 μm.
10 . The semiconductor device of claim 1 , wherein an elastic modulus of the buffer layer is smaller than an elastic modulus of the semiconductor substrate.
11 . A semiconductor device comprising: a semiconductor substrate; an element layer on the semiconductor substrate; a wiring layer on the element layer; and a first buffer layer provided between the semiconductor substrate and the element layer or between the element layer and the wiring layer, wherein the first buffer layer includes first voids and second voids spaced apart from each other, wherein each of the first voids is formed by a first recess extending from an upper surface of the first buffer layer towards an inside of the first buffer layer, wherein each of the second voids is formed by a second recess extending from a lower surface of the first buffer layer towards an inside of the first buffer layer, and wherein the plurality of second voids include a plurality of pairs of adjacent second voids, and wherein, in a plan view, each of the first voids of the first buffer layer is disposed between a corresponding one of the plurality of pairs of adjacent second voids.
12 . The semiconductor device of claim 11 , wherein the first buffer layer includes an insulating polymer.
13 . The semiconductor device of claim 11 , wherein the first buffer layer is interposed between the semiconductor substrate and the element layer.
14 . The semiconductor device of claim 11 , wherein: a height level of bottom surfaces of the first voids is higher than a height level of bottom surfaces of the second voids, and a distance between the height level of the bottom surfaces of the first voids and the height level of the bottom surfaces of the second voids is 1 μm to 2 μm.
15 . The semiconductor device of claim 11 , wherein a width of each of the first voids and the second voids is 3 μm to 10 μm.
16 . The semiconductor device of claim 11 , further comprising: a second buffer layer covering the lower surface of the first buffer layer; and a third buffer layer covering the upper surface of the first buffer layer, wherein a lower surface of the second buffer layer and an upper surface of the third buffer layer are flat.
17 . The semiconductor device of claim 11 , wherein: the element layer includes a passive device, the wiring layer includes a connection pad protruding above an upper surface of the wiring layer, the first buffer layer is interposed between the element layer and the wiring layer, the passive device is electrically connected to the connection pad through a through-via penetrating the first buffer layer, and the first voids and the second voids of the first buffer layer are horizontally spaced apart from the through-via in a plan view.
18 . A semiconductor device comprising: a package substrate; a semiconductor chip disposed on the package substrate; and a molding layer surrounding the semiconductor chip on the package substrate, wherein the semiconductor chip includes: a semiconductor substrate, a wiring layer on the semiconductor substrate, and a buffer layer interposed between the semiconductor substrate and the wiring layer, wherein the buffer layer includes: a first buffer layer including a plurality of first voids spaced apart from each other, and a second buffer layer provided on the first buffer layer, wherein the second buffer layer includes a plurality of second voids spaced apart from each other, wherein, in a plan view, the first voids and the second voids are alternately arranged, spaced apart from each other by a first distance, and repetitively arranged in a first direction and a second direction that intersect each other, and wherein an elastic modulus of the buffer layer is smaller than an elastic modulus of the semiconductor substrate.
19 . The semiconductor device of claim 18 , wherein the buffer layer further includes a third buffer layer interposed between the first buffer layer and the second buffer layer, and wherein a thickness of the third buffer layer is 1 μm to 2 μm.
20 . The semiconductor device of claim 18 , wherein the semiconductor chip further includes an element layer provided between the semiconductor substrate and the wiring layer, wherein the element layer further includes a capacitor, and wherein the capacitor includes: a first electrode, a capacitor dielectric layer covering the first electrode with a uniform thickness, and a second electrode covering the first electrode on the capacitor dielectric layer, and wherein the buffer layer is interposed between the semiconductor substrate and the element layer.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 of Korean Patent Application No. 10-2024-0156294, filed on Nov. 6, 2024, the entire contents of which are hereby incorporated by reference. BACKGROUND The present disclosure herein relates to a semiconductor chip and a semiconductor package. With the development of the electronics industry, electronic components are required to have higher-level functions, higher speed, and smaller size. For example, semiconductor devices in a semiconductor package are required to have higher reliability, higher speed, and/or more functions. In order to satisfy such required characteristics, structures in a semiconductor package are more complicated and more highly integrated. As the structures in a semiconductor package are more highly integrated, the reliability and mechanical stability of the semiconductor package may more significantly deteriorate. Therefore, researches are being carried out actively to improve the reliability and stability of a semiconductor package. SUMMARY The present disclosure provides a semiconductor device with improved mechanical characteristics. The semiconductor device may be a semiconductor chip or package. The present disclosure also provides a semiconductor chip and a semiconductor package with improved driving stability. The purposes of the present invention are not limited to the above-mentioned purposes, and other purposes not mentioned would be clearly understood by those skilled in the art from the disclosure below. An embodiment of the inventive concept provides a semiconductor device including: a semiconductor substrate; an element layer on the semiconductor substrate; a wiring layer on the element layer; and a buffer layer provided between the semiconductor substrate and the element layer or between the element layer and the wiring layer. The buffer layer includes: a first buffer layer including a plurality of first voids spaced apart from each other, and a second buffer layer provided on the first buffer layer and including a plurality of second voids spaced apart from each other, The plurality of second voids are disposed at a different height level than the plurality of first voids. The plurality of second voids include a plurality of pairs of adjacent second voids. In a plan view, each of the first voids of the buffer layer is disposed between a corresponding one of the plurality of pairs of adjacent second voids. In an embodiment of the inventive concept, a semiconductor device includes: a semiconductor substrate; an element layer on the semiconductor substrate; a wiring layer on the element layer; and a first buffer layer provided between the semiconductor substrate and the element layer or between the element layer and the wiring layer, wherein the first buffer layer includes first voids and second voids spaced apart from each other. Each of the first voids is formed by a first recess extending from an upper surface of the first buffer layer towards an inside of the first buffer layer. Each of the second voids is formed by a second recess extending from a lower surface of the first buffer layer towards the inside of the first buffer layer. The plurality of second voids include a plurality of pairs of adjacent second voids. In a plan view, each of the first voids of the first buffer layer is disposed between a corresponding one of the plurality of pairs of adjacent second voids. In an embodiment of the inventive concept, a semiconductor device includes: a package substrate; a semiconductor chip disposed on the package substrate; and a molding layer surrounding the semiconductor chip on the package substrate, wherein the semiconductor chip includes: a semiconductor substrate; a wiring layer on the semiconductor substrate; and a buffer layer interposed between the semiconductor substrate and the wiring layer, wherein the buffer layer includes: a first buffer layer including a plurality of first voids spaced apart from each other; and a second buffer layer provided on the first buffer layer, wherein the second buffer layer includes a plurality of second voids spaced apart from each other. The first voids and the second voids are alternately arranged, spaced apart from each other by a predetermined distance, and repetitively arranged in a first direction and a second direction that intersect each other in a plan view. An elastic modulus of the buffer layer is smaller than an elastic modulus of the semiconductor substrate. BRIEF DESCRIPTION OF THE FIGURES The accompanying drawings are included to provide a further understanding of the inventive concept, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the inventive concept and, together with the description, serve to explain principles of the inventive concept. In the drawings: FIG. 1 is a cross-sectional view for describing a semiconductor package acco