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US-20260130276-A1 - SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME

US20260130276A1US 20260130276 A1US20260130276 A1US 20260130276A1US-20260130276-A1

Abstract

A semiconductor device package and a method of manufacturing a semiconductor device package are provided. The semiconductor device package includes a carrier, a first component, a second component, and a protective element. The first component and the second component are arranged side by side in a first direction over the carrier. The protective element is disposed over a top surface of the carrier and extending from space under the first component toward a space under the second component. The protective element includes a first portion and a second portion protruded oppositely from edges of the first component by different distances, and the first portion and the second portion are arranged in a second direction angled with the first direction.

Inventors

  • Jung Jui KANG
  • SHIH-YUAN SUN
  • Chieh-Chen Fu

Assignees

  • ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Dates

Publication Date
20260507
Application Date
20251231

Claims (20)

  1. 1 . A semiconductor device package, comprising: a carrier; a first component and a second component adjacent to each other; and a first protective element at least partially disposed under the first component, wherein the first protective element comprises a first portion and a second portion protruding from opposite edges of the first component by different distances in a top view.
  2. 2 . The semiconductor device package of claim 1 , wherein the first component is a photonic IC.
  3. 3 . The semiconductor device package of claim 2 , wherein the first protective element comprises a third portion protruding from an edge of the second component by a first distance greater than a second distance by which the first portion protrudes from one of the opposite edges of the first component.
  4. 4 . The semiconductor device package of claim 1 , wherein the first protective element comprises a stepped structure.
  5. 5 . The semiconductor device package of claim 4 , wherein the stepped structure comprises a step depth in the top view.
  6. 6 . The semiconductor device package of claim 1 , wherein the second component has a corner adjacent to the first component and wherein the first protective element has a taper profile adjacent to the corner in the top view.
  7. 7 . The semiconductor device package of claim 6 , wherein the taper profile narrows toward the corner of the second component.
  8. 8 . The semiconductor device package of claim 7 , wherein, in the top view, the taper profile comprises a first edge and a second edge extending between the corner and an edge of the carrier, wherein the second edge is angled with the first edge.
  9. 9 . The semiconductor device package of claim 1 , wherein, in the top view, the first portion has a first corner and a second corner protruding from a first edge of the opposite edges, and, in a first direction parallel to the first edge, a first length between the first corner and the second corner is shorter than a second length of the first edge.
  10. 10 . The semiconductor device package of claim 9 , wherein, in the top view, the second portion has a third corner and a fourth corner protruding from a second edge of the opposite edges, and, in the first direction, a third length between the third corner and the fourth corner is shorter than a fourth length of the second edge, and wherein the first length is different from the third length.
  11. 11 . A semiconductor device package, comprising: a photonic component and an electronic component adjacent to each other; and a protective element comprising a first portion covering a portion of the photonic component and a second portion covering a portion of the electronic component, wherein a first top surface of the first portion has a first elevation with respect to a bottom surface of the electronic component and a second top surface of the second portion has a second elevation with respect to the bottom surface of the electronic component, and wherein the first elevation is lower than the second elevation.
  12. 12 . The semiconductor device package of claim 11 , wherein the protective element comprises a third portion connected to the first portion and the second portion, wherein the third portion has a third top surface at a third elevation lower than the first elevation, and wherein the third elevation is lower than the bottom surface of the electronic component.
  13. 13 . The semiconductor device package of claim 11 , further comprising a carrier supporting the photonic component and an electronic component, wherein a first gap defined by the carrier and the photonic component is smaller than a second gap defined by the carrier and the electronic component.
  14. 14 . The semiconductor device package of claim 11 , wherein the first portion and the second portion are between the photonic component and the electronic component.
  15. 15 . The semiconductor device package of claim 11 , further comprising a plurality of conductive connection elements disposed under the photonic component and an interposer electrically connecting the photonic component to the conductive connection elements.
  16. 16 . A semiconductor device package, comprising: a carrier with an opening; a photonic component and an electronic component adjacent to each other; a first component disposed over the photonic component; and a protective element covering a portion of the photonic component and a portion of the electronic component, wherein the photonic component is disposed above the opening in a cross-section and located between the electronic component and the opening in a top view.
  17. 17 . The semiconductor device package of claim 16 , wherein the first component is an electronic IC.
  18. 18 . The semiconductor device package of claim 16 , wherein a first distance between the photonic component and the opening is less than a second distance between the photonic component and an edge of the carrier, from which the opening is recessed.
  19. 19 . The semiconductor device package of claim 16 , wherein the protective element comprises a first portion covering a part of a first edge of the photonic component and a second portion covering a part of a first edge of the electronic component, wherein the first portion has a thickness extending from a top surface of the carrier to a top surface of the first portion, the second portion has a thickness extending from the top surface of the carrier to a top surface of the second portion, and the thickness of the first portion is less than the thickness of the second portion.
  20. 20 . The semiconductor device package of claim 16 , wherein the protective element comprises a first portion between the photonic component and the opening.

Description

CROSS REFERENCE TO RELATED APPLICATION This application is a continuation of U.S. patent application Ser. No. 17/876,466, filed Jul. 28, 2022, the content of which is incorporated herein by reference in its entirety. BACKGROUND 1. Technical Field The present disclosure relates generally to a semiconductor device package and a method of manufacturing a semiconductor device package. 2. Description of the Related Art Silicon photonics and optical engines with integration of at least an electronic IC (EIC) and a photonic IC (PIC) have advantages of high transmission speed and low power loss, and thus are applied in various areas. The electronic IC and the photonic IC may be arranged in a side-by-side fashion. Therefore, the transmission path between the electronic IC and the photonic IC may be relatively long. However, when the distance between the electronic IC and the photonic IC is reduced to solve the aforesaid issue, an underfill in the relatively small gap may overflow to adversely affect performance of the integrated device. SUMMARY In one or more embodiments, a semiconductor device package includes a carrier, a first component, a second component, and a protective element. The first component and the second component are arranged side by side in a first direction over the carrier. The protective element is disposed over a top surface of the carrier and extending from a space under the first component toward a space under the second component. The protective element includes a first portion and a second portion protruded oppositely from edges of the first component by different distances, and the first portion and the second portion are arranged in a second direction angled with the first direction. In one or more embodiments, a semiconductor device package includes a carrier, a photonic component, an electronic component, and a protective element. The photonic component and the electronic component are arranged side by side over the carrier. The protective element includes a first portion covering a portion of the photonic component and a second portion covering a portion of the electronic component. The first portion has a thickness extending from a top surface of the carrier to a top surface of the first portion, the second portion has a thickness extending from the top surface of the carrier to a top surface of the second portion, and the thickness of the first portion is less than the thickness of the second portion. In one or more embodiments, method of manufacturing a semiconductor device package includes bonding a first component and a second component to a carrier, wherein the first component and the second component are arranged side by side in a first direction; and applying a protective material over the carrier substantially along the first direction. The protective material includes a first portion adjacent to the first component and a second portion adjacent to the second component, and an amount of the first portion is less than an amount of the second portion. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. It is noted that various features may not be drawn to scale, and the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 is a top view of a semiconductor device package in accordance with some embodiments of the present disclosure; FIG. 1A is a cross-section of a semiconductor device package in accordance with some embodiments of the present disclosure; FIG. 1A-1 is a cross-section of a semiconductor device package in accordance with some embodiments of the present disclosure; FIG. 1A-2 is a cross-section of a semiconductor device package in accordance with some embodiments of the present disclosure; FIG. 1B is a cross-section of a semiconductor device package in accordance with some embodiments of the present disclosure; FIG. 1C is a cross-section of a semiconductor device package in accordance with some embodiments of the present disclosure; FIG. 1D is a cross-section of a semiconductor device package in accordance with some embodiments of the present disclosure; FIG. 2A is a cross-section of a semiconductor device package in accordance with some embodiments of the present disclosure; FIG. 2B is a cross-section of a semiconductor device package in accordance with some embodiments of the present disclosure; FIG. 2C is a cross-section of a semiconductor device package in accordance with some embodiments of the present disclosure; FIG. 3A is a top view of a semiconductor device package in accordance with some embodiments of the present disclosure; FIG. 3B is a cross-section of a semiconductor device package in accordance with some embodiments of the present disclosure; FIG. 4 is a top view of a semiconductor device package in accordance with some embodiments of the present disclosure; FIG. 4A is a cross-sectio