US-20260130278-A1 - DIE STRUCTURE, PACKAGE STRUCTURE AND METHOD FOR FABRICATING DIE STRUCTURE

US20260130278A1US 20260130278 A1US20260130278 A1US 20260130278A1US-20260130278-A1

Abstract

A die structure is provided. The die structure includes a base having a first device region and a second device region adjacent to the first device region. The die structure includes a plurality of first device cores stacked on the first device region of the base. The die structure includes a plurality of second device cores stacked on the second device region of the base. The die structure includes a top core over the first device cores and the second device cores. An interconnect structure is embedded in the top core and electrically connected to the first device cores and the second device cores. The die structure also includes a die molding material formed over the base and encapsulating the first device cores, the second device cores, and the top core.

Inventors

Chieh-Lung Lai
Meng-Liang Lin
Hsien-Wei Chen
Kathy Wei Yan

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date: 20260507
Application Date: 20241101

Claims (20)

1 . A die structure, comprising: a base having a first device region and a second device region adjacent to the first device region; a plurality of first device cores stacked on the first device region of the base; a plurality of second device cores stacked on the second device region of the base; a top core over the first device cores and the second device cores, wherein an interconnect structure is embedded in the top core and electrically connected to the first device cores and the second device cores; and a die molding material formed over the base and encapsulating the first device cores, the second device cores, and the top core.
2 . The die structure as claimed in claim 1 , further comprising: a first plurality of conductive features electrically connected to the first device cores; and a second plurality of conductive features electrically connected to the second device cores, wherein the first plurality and the second plurality of conductive features are electrically connected to the interconnect structure in the top core.
3 . The die structure as claimed in claim 2 , wherein the interconnect structure comprises a connecting wire connected to one of the first plurality of conductive features and one of the second plurality of conductive features.
4 . The die structure as claimed in claim 3 , wherein a width of the connecting wire is less than or equal to about 10 μm in a direction perpendicular to a normal direction of the base.
5 . The die structure as claimed in claim 3 , wherein the connecting wire extends in different directions that are not parallel to each other.
6 . The die structure as claimed in claim 3 , wherein the interconnect structure comprises a bulk portion located around the connecting wire, and the bulk portion extends over the first device region and the second device region.
7 . The die structure as claimed in claim 6 , wherein a plurality of openings are formed in the bulk portion.
8 . The die structure as claimed in claim 6 , wherein the bulk portion comprises a chamfer structure facing the connecting wire.
9 . The die structure as claimed in claim 6 , wherein the first plurality and the second plurality of conductive features are electrically connected to the bulk portion.
10 . The die structure as claimed in claim 3 , wherein the interconnect structure comprises a plurality of dummy patterns electrically isolated from the connecting wire.
11 . A package structure, comprising: a device die bonded to a package substrate, wherein the device die comprises: a base having a first device region and a second device region adjacent to the first device region; a plurality of first device cores stacked on the first device region of the base; a plurality of second device cores stacked on the second device region of the base; a top core over the first device cores and the second device cores, wherein an interconnect structure is embedded in the top core and electrically connected to the first device cores and the second device cores; and a die molding material formed over the base and encapsulating the first device cores, the second device cores, wherein the die molding material exposes a top surface of the top core; and a package molding material over the package substrate and around the device die.
12 . The package structure as claimed in claim 11 , wherein in a plan view, a ratio of an area of the interconnect structure to an area of the top core is ranged from about 40% to about 80%.
13 . The package structure as claimed in claim 11 , wherein the interconnect structure comprises a plurality of metallization layers, and a thickness of each of the metallization layers is ranged from about 2 μm to about 5 μm in a direction parallel to a normal direction of the base.
14 . The package structure as claimed in claim 11 , wherein a thickness of the top core is ranged from about 50 μm to about 800 μm in a direction parallel to a normal direction of the base.
15 . A method for fabricating a die structure, comprising: stacking a plurality of first device cores over a first device region of a base; stacking a plurality of second device cores over a second device region of the base, wherein the first device region is adjacent to the second device region; bonding a top core over the first device cores and the second device cores, wherein an interconnect structure is embedded in the top core and electrically connected to the first device cores and the second device cores; and forming a die molding material formed over the base and encapsulating the first device cores, the second device cores, wherein a top surface of the die molding material is substantially level with a top surface of the top core.
16 . The method as claimed in claim 15 , further comprising: forming a first plurality of conductive features electrically connected to the first device cores; and forming a second plurality of conductive features electrically connected to the second device cores, wherein the first plurality and the second plurality of conductive features are electrically connected to the interconnect structure in the top core.
17 . The method as claimed in claim 15 , further comprising: forming the interconnect structure in the top core before the top core is bonded over the first device cores and the second device cores, wherein forming the interconnect structure comprises forming a metallization layer in the top core, and in a plan view, a ratio of an area of the metallization layer to an area of the top core is ranged from about 40% to about 80%.
18 . The method as claimed in claim 17 , wherein forming the interconnect structure in the top core further comprises: forming a connecting wire connected to one of the first plurality of conductive features and one of the second plurality of conductive features.
19 . The method as claimed in claim 18 , wherein forming the interconnect structure in the top core further comprises: forming a bulk portion around the connecting wire, wherein the bulk portion extends over the first device region and the second device region, and a plurality of openings are formed in the bulk portion.
20 . The method as claimed in claim 17 , wherein forming the interconnect structure in the top core further comprises: forming a plurality of dummy patterns located around and electrically isolated from the connecting wire.

Description

BACKGROUND Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. Many integrated circuits are typically manufactured on a single semiconductor wafer, and individual dies on the wafer are singulated by sawing between the integrated circuits along a scribe line. The individual dies are typically packaged separately, in multi-chip modules, for example, or in other types of packaging. Although existing methods of fabricating semiconductor structures have generally been adequate for their intended purposes, they have not been entirely satisfactory in all respects. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIGS. 1A through 1D illustrates cross-sectional views of intermediate steps during a process for fabricating a die structure in accordance with some embodiments. FIGS. 2A through 2K illustrates cross-sectional views of intermediate steps during a process for fabricating a package structure in accordance with some embodiments. FIG. 3 illustrates a cross-sectional view of the package structure in accordance with some embodiments. FIG. 4 illustrates a plan view of the die structure in accordance with some embodiments. FIG. 5 illustrates a plan view of the die structure in accordance with some embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Some variations of the embodiments are described. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. It should be understood that additional operations can be provided before, during, and after the method, and some of the operations described can be replaced or eliminated for other embodiments of the method. Embodiments of die structures, package structures and methods for fabricating the die structures are provided. The die structure includes a top core over the first device cores stacked on the first device region of the base and the second device cores stacked on the second device region of the base. An interconnect structure is embedded in the top core and electrically connected to the first device cores and the second device cores. As a result, the different stacks of device cores may be connected and operate together to enhance the performance of the die structure. In addition, since multiple stacks of device cores are integrated, the formation of the package structure can be simplified. Furthermore, a bulk top die connecting the device cores in adjacent device regions of the die structure replaces the molding material between different stacks of device cores, and therefore thermal dissipation and warpage control for the package structure may be improved. FIGS. 1A through 1D illustrates cross-sectional views of intermediate steps during a process for fabricating a die structure 50 in accordance with some embodiments. As shown in FIG. 1A, a base 52 is provided and have a first device region 52A and a second device region 52B that is adjacent to the first device region 52A. For example, the base 52 includes a semiconductor material, such as silicon, germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAs