US-20260130279-A1 - SEMICONDUCTOR DEVICE AND METHODS OF FORMATION

US20260130279A1US 20260130279 A1US20260130279 A1US 20260130279A1US-20260130279-A1

Abstract

A first integrated circuit (IC) die and a second IC die are bonded together in a stacked arrangement in a device package. The second IC die includes at least one bonding structure that is bonded to the first IC die. A barrier layer on sidewalls of a top portion of the bonding structure is removed and replaced with a dielectric liner that is formed on the sidewalls after the bonding structure is formed. The dielectric liner has a material removal rate (e.g., for processes such as CMP, grinding, and/or chemical-based surface cleaning) that is closer to the material removal rate of the bonding structure than the material removal rate of the barrier liner. This reduces the likelihood of the formation of voids in the bond between the first IC die and the second IC die that might otherwise occur due to excessive material removal from the bonding structure.

Inventors

TZU JUNG TIEN
Jen-Yuan Chang

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date: 20260507
Application Date: 20241105

Claims (20)

1 . A method, comprising: forming one or more integrated circuit (IC) devices in a substrate of an IC die; forming a plurality of vertically-arranged metallization layers above the one or more IC devices; forming a metal pad structure on a top-most metallization layer of the plurality of vertically-arranged metallization layers; forming a recess through a first layer and a second layer above the metal pad structure; forming a bonding structure in the recess such that the bonding structure lands on the metal pad structure; removing the second layer from around the bonding structure; and forming, above the first layer, a bonding dielectric layer around the bonding structure.
2 . The method of claim 1 , wherein the first layer comprises a dielectric layer; and wherein the second layer comprises a photoresist layer.
3 . The method of claim 1 , wherein forming the bonding structure comprises: forming a via portion of the bonding structure in a first portion of the recess through the first layer; and forming a pad portion of the bonding structure in a second portion of the recess through the second layer.
4 . The method of claim 3 , wherein the second layer is above the first layer; and wherein the pad portion is above the via portion.
5 . The method of claim 3 , wherein forming the bonding structure comprises: forming a barrier liner on sidewalls of the first portion of the recess and on sidewalls of the second portion of the recess; forming the via portion of the bonding structure such that the barrier liner is between sidewalls of the via portion and the sidewalls of the first portion of the recess; and forming the pad portion of the bonding structure such that the barrier liner is between sidewalls of the pad portion and the sidewalls of the second portion of the recess.
6 . The method of claim 5 , further comprising: removing the barrier liner from the sidewalls of the pad portion of the bonding structure.
7 . The method of claim 1 , further comprising: forming a dielectric liner directly on sidewalls of the bonding structure after removing the second layer from around the bonding structure, wherein the dielectric liner has a dielectric constant that is less than a dielectric constant of tantalum nitride (TaN).
8 . A method, comprising: forming one or more integrated circuit (IC) devices in a substrate of an IC die; forming a plurality of vertically-arranged metallization layers above the one or more IC devices; forming a metal pad structure on a top-most metallization layer of the plurality of vertically-arranged metallization layers; forming a first portion of a recess through a first layer above the metal pad structure; forming a second portion of the recess through a second layer above the metal pad structure and below the first layer; forming a bonding via in the second portion of the recess such that the bonding via lands on the metal pad structure; forming a bonding pad in the first portion of the recess such that the bonding pad lands on the bonding via; removing the first layer from around the bonding pad; and forming, above the second layer, a bonding dielectric layer around the bonding pad.
9 . The method of claim 8 , further comprising: forming a tantalum-based barrier liner on sidewalls of the recess, wherein forming the bonding via comprises forming the bonding via on the tantalum-based barrier liner, and wherein forming the bonding pad comprises forming the bonding pad such that the tantalum-based barrier liner is between the sidewalls of the bonding pad and the first layer.
10 . The method of claim 9 , further comprising: removing the tantalum-based barrier liner from the sidewalls of the bonding pad; and forming a silicon-based dielectric liner on the sidewalls of the bonding pad.
11 . The method of claim 10 , wherein forming the bonding dielectric layer comprises: forming the bonding dielectric layer such that the silicon-based dielectric liner is between the sidewalls of the bonding pad and the bonding dielectric layer.
12 . The method of claim 8 , wherein removing the first layer from around the bonding pad comprises: performing a chemical stripping operation to remove the first layer, or performing a plasma ashing operation to remove the first layer.
13 . The method of claim 8 , wherein forming the first portion of the recess comprises: forming the first portion of the recess by photolithography patterning; and wherein forming the second portion of the recess comprises: forming the second portion of the recess by etching.
14 . A device package, comprising: a first integrated circuit (IC) die; and a second IC die bonded to and vertically arranged with the first IC die, wherein the first IC die comprises: a bonding via coupled to a metal pad structure that is vertically adjacent to the bonding via; a barrier liner on sidewalls of the bonding via; a bonding pad coupled to the bonding via, wherein the bonding pad is vertically adjacent to the bonding via, and wherein the bonding via is vertically between the bonding pad and the metal pad structure; and a dielectric layer on sidewalls of the bonding pad, wherein the barrier liner and the dielectric layer comprise different materials.
15 . The device package of claim 14 , wherein the barrier liner comprises at least one of: tantalum (Ta), or tantalum nitride (TaN); and wherein the dielectric layer comprises at least one of: a silicon oxide (SiO x ), a silicon nitride (Si x N y ), a silicon oxynitride (SiON), a silicon oxycarbide (SiOC), or a silicon carbonitride (SiCN).
16 . The device package of claim 14 , wherein the bonding pad is bonded to a through-substrate interconnect structure included in the second IC die.
17 . The device package of claim 14 , wherein the bonding pad is bonded to a bonding dielectric layer included in the second IC die.
18 . The device package of claim 14 , wherein the first IC die further comprises: another bonding via coupled to the metal pad structure that is vertically adjacent to the other bonding via; another barrier liner on sidewalls of the other bonding via; and another bonding pad coupled to the other bonding via, wherein the other bonding pad is vertically adjacent to the other bonding via, wherein the other bonding via is vertically between the other bonding pad and the metal pad structure, and wherein the dielectric layer is on sidewalls of the other bonding pad.
19 . The device package of claim 14 , wherein the metal pad structure comprises a first metal material; wherein the bonding via and the bonding pad comprise a second metal material; and wherein the first metal material and the second metal material are different metal materials.
20 . The device package of claim 14 , wherein a top view shape of the bonding pad comprises at least one of: an approximate circle shape, an approximate rectangle shape, an approximate hexagon shape, or an approximate L-shape.

Description

BACKGROUND A semiconductor die package may include a plurality of integrated circuit (IC) dies that offer a variety of functionalities. Examples of IC dies include a system-on-chip (SoC) IC die, a dynamic random access memory (DRAM) IC die, a logic IC die, and/or a high bandwidth memory (HBM) IC die, among other examples. Some semiconductor die packages include an interposer that enables IC dies to be laterally arranged on the interposer. In some semiconductor die packages, IC dies are vertically arranged using three-dimensional (3D) packaging techniques such as direct bonding. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIGS. 1A-1C are diagrams of an example of a semiconductor die package described herein. FIGS. 2A-2D illustrate example top view shapes for a bonding pad described herein. FIGS. 3A-3H are diagrams of an example implementation of forming an integrated circuit (IC) die described herein. FIGS. 4A-4K are diagrams of an example implementation of forming an IC die described herein. FIGS. 5A-5H are diagrams of an example implementation of forming a semiconductor die package described herein. FIGS. 6-9 illustrate example implementations of bonding arrangements for bonding a bonding pad of an IC die to another IC die in a semiconductor die package described herein. FIG. 10 is a flowchart of an example process associated with forming a semiconductor device described herein. FIG. 11 is a flowchart of an example process associated with forming a semiconductor device described herein. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. To enable signals and/or power to be routed between a first integrated circuit (IC) die and a second IC die that are bonded together in a stacked arrangement in a device package, one or more through-substrate interconnect structures may be included through a substrate layer of the first IC die. The through-substrate interconnect structure(s) (sometimes referred to as through-silicon vias or through-substrate vias (TSVs)) may extend between, and may be electrically coupled to, conductive structures on a front side and on a back side of the substrate layer. The conductive structure(s) on the back side of the substrate layer coupled to the through-substrate interconnect structure(s) may be bonded with bonding structures (e.g., bonding vias, bonding pads) of the second IC die. The bonding structures of the second IC die may be formed of a metal material such as copper (Cu). The metal material of the bonding structures may be susceptible to material migration into the surrounding dielectric layers. Therefore, a barrier liner may be included between the bonding structures and the surrounding dielectric layers to prevent, minimize, and/or otherwise reduce the likelihood of migration of material into the surrounding dielectric layers, which might otherwise result in current leakage from the bonding structures. Barrier liners for material migration blocking are typically formed of hard materials such as tantalum nitride (TaN) and/or titanium nitride (TiN) that are highly resistant to material remova