US-20260130280-A1 - STACKED PACKAGE DEVICE WITH INTERMEDIATE SUBSTRATE

Abstract

A stacked package device has a first package and a second package vertically stacked and electrically connected to each other. One or each of the first package and the second package includes a first substrate, a second substrate and an intermediate substrate. A first flip-chip and a second flip-chip are respectively mounted on opposite surfaces of the first substrate and the second substrate. The intermediate substrate is electrically connected between the opposite surfaces of the first substrate and the second substrate for signal transmission between the first flip-chip and the second flip-chip. The use of the intermediate substrate avoids the structure damage resulting from thermal stress. Since no encapsulant is provided to cover each flip-chip, the problem of separation between the encapsulant and the substrates is avoided.

Inventors

• HUNG HSIN HSU
• LIEN CHIA CHANG

Assignees

• POWERTECH TECHNOLOGY INC.

Dates

Publication Date

20260507

Application Date

20241105

Priority Date

20231220

Claims (10)

1. 1 . A stacked package comprising: a first package; a second package connected to the first package in a stacked arrangement, the second package comprising: a first substrate having an outer surface and an inner surface opposite to each other, the outer surface electrically connected to the first package, and a first flip-chip electrically mounted on the inner surface; a second substrate having an outer surface and an inner surface opposite to each other, the inner surface of the second substrate facing the inner surface of the first substrate, and a second flip-chip electrically mounted on the inner surface of the second substrate; an intermediate substrate electrically connected between the inner surface of the first substrate and the inner surface of the second substrate, underfill filling space between the intermediate substrate and the first substrate and space between the intermediate substrate and the second substrate, an opening being formed through the intermediate substrate at a position corresponding to the first flip-chip and the second flip-chip; and multiple external connecting members provided on the outer surface of the second substrate.
2. 2 . The stacked package as claimed in claim 1 comprising: a first annular groove formed in the inner surface of the first substrate and around the first flip-chip; and a second annular groove formed in the inner surface of the second substrate and around the second flip-chip.
3. 3 . The stacked package as claimed in claim 1 comprising: a first annular dam formed on the inner surface of the first substrate and around the first flip-chip; and a second annular dam formed on the inner surface of the second substrate and around the second flip-chip.
4. 4 . The stacked package as claimed in claim 1 , wherein each of the inner surfaces of the first flip-chip and the second flip-chip is a flat surface; non-active surfaces of the first flip-chip and the second flip-chip face to each other but are separated by a gap.
5. 5 . The stacked package as claimed in claim 1 , wherein the opening between the first substrate and the second substrate is surrounded by the underfill to form a chip accommodating chamber; and the first flip-chip and the second flip-chip are placed in the chip accommodating chamber.
6. 6 . The stacked package as claimed in claim 1 , wherein non-active surfaces and lateral surfaces of both the first flip-chip and the second flip-chip are exposed in the chip accommodating chamber.
7. 7 . The stacked package as claimed in claim 1 , wherein the intermediate substrate has an upper surface and a lower surface opposite to each other, multiple upper contacts are formed on the upper surface, multiple lower contacts are formed on the lower surface and electrically connected to the upper contacts through an inner redistribution layer in the intermediate layer; multiple inner pads and outer pads are respectively formed on the inner surface and the outer surface of the first substrate, and the inner pads are electrically connected to the respective outer pads through a first redistribution layer in the first substrate; and multiple inner pads and outer pads are respectively formed on the inner surface and the outer surface of the second substrate, and the inner pads of the second substrate are electrically connected to the respective outer pads of the second substrate through a second redistribution layer in the second substrate.
8. 8 . The stacked package device as claimed in claim 7 , wherein pitches between the upper contacts of the intermediate substrate are different from pitches between the outer pads of the first substrate; and pitches between the lower contacts of the intermediate substrate are different from pitches between the outer pads of the second substrate.
9. 9 . The stacked package device as claimed in claim 7 , wherein pitches between the upper contacts of the intermediate substrate are smaller than pitches between the outer pads of the first substrate; and pitches between the lower contacts of the intermediate substrate are smaller than pitches between the outer pads of the second substrate.
10. 10 . The stacked package device as claimed in claim 1 , wherein the intermediate substrate has a thickness being greater than a sum of heights of the first flip-chip and the second flip-chip.

Description

CROSS REFERENCE TO RELATED APPLICATIONS This non-provisional application claims the benefit under 35 U.S.C. § 119(a) to Patent Application No. 112149748 filed in Taiwan on Dec. 20, 2023, which is hereby expressly incorporated by reference into the present application. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stacked package device, particularly to a stacked package device comprising an intermediate substrate interconnected between different substrates for electrical connection. 2. Description of the Related Art In order to integrate different types of or multiple package elements, package on package (PoP) technology is proposed to stack multiple packages into a miniaturized component to reduce space occupation as much as possible in electronic products. With reference to FIG. 4, according to conventional PoP technology, a top package 100 is placed above and electrically connected to a bottom package 200. Both the top package 100 and the bottom package 200 contain a respective chip. For a high bandwidth PoP, the bottom package 200 may have a top substrate 201, a bottom substrate 202 and a plurality of conductive pillars 230 vertically interconnected between the top substrate 201 and the bottom substrate 202. An encapsulant 240 (EMC) is provided to fill space between the top substrate 201 and the bottom substrate 202 and encapsulate the chip inside the bottom package 200. The conductive pillars 230 provided between the top substrate 201 and the bottom substrate 202 are usually formed by the electroplating process. However, the conductive pillars 230 may have voids formed therein during the electroplating process. When the conductive pillars 230 are subjected to thermal stress, the voids may cause damage to the conductive pillars 230 and deteriorate their electrical transmission capability. Further, because the encapsulant 240 and the two substrates 201, 202 have different coefficients of thermal expansion (CTE), the separation between the encapsulant 240 and the two substrates 201, 202 may occur when they are heated. SUMMARY OF THE INVENTION An objective of the present disclosure is to provide a stacked package device free from encapsulant so as to mitigate possible damages caused by thermal stress to the structure of the stacked package. The stacked package device comprises a first package and a second package. The second package is connected to the first package in a stacked arrangement and comprises: a first substrate having an outer surface and an inner surface opposite to each other, the outer surface electrically connected to the first package, and a first flip-chip electrically mounted on the inner surface;a second substrate having an outer surface and an inner surface opposite to each other, the inner surface of the second substrate facing the inner surface of the first substrate, and a second flip-chip electrically mounted on the inner surface of the second substrate;an intermediate substrate electrically connected between the inner surface of the first substrate and the inner surface of the second substrate, underfill filling space between the intermediate substrate and the first substrate and space between the intermediate substrate and the second substrate, an opening being formed through the intermediate substrate at a position corresponding to the first flip-chip and the second flip-chip; andmultiple external connecting members provided on the outer surface of the second substrate. Based on the above, the stacked package device of the invention, via the intermediate substrate to electrically connect the first substrate and the second substrate, rather than forming copper pillar by electroplating, the problem of structural damage to the copper pillar due to thermal stress can be avoided. Furthermore, no encapsulant (EMC) is provided between the first substrate and the second substrate to cover chips, which prevents the encapsulant from separating from the substrates. Other objectives, advantages and novel features of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross section view of a stacked package device according to an embodiment of the invention; FIG. 2 is a cross section view of a stacked package device according to another embodiment of the invention; FIG. 3 is a cross section view of a stacked package device according to yet another embodiment of the invention; and FIG. 4 is a cross section view of a conventional stacked package device. DETAILED DESCRIPTION OF THE INVENTION Directional terms as used herein, for example, up, down, right, left, front, back, top, bottom are made only with reference to the figures as illustrated and are not intended to imply absolute orientation unless otherwise specified. With reference to FIG. 1, according to one embodiment of the invention, a stacked package device compris