US-20260130281-A1 - PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME

US20260130281A1US 20260130281 A1US20260130281 A1US 20260130281A1US-20260130281-A1

Abstract

A package structure includes a circuit substrate and a semiconductor package disposed on and electrically connected to the circuit substrate. The semiconductor package includes and interconnection structure, first passive devices, second passive devices and bump structures. The first passive devices are electrically connected to the interconnection structure, and arranged as a first pattern in between the interconnection structure and the circuit substrate. The second passive devices are electrically connected to the interconnection structure, and arranged as a second pattern in between the interconnection structure and the circuit substrate, wherein the second pattern is different from the first pattern. The bump structures are electrically connecting the interconnection structure to the circuit substrate and laterally surrounding the first passive devices and the second passive devices.

Inventors

Cheng-Xuan Wu
Chia-Peng Sun
Kai-Cheng Chen
Wen-Yi Lin
Zhihua Zou

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date: 20260507
Application Date: 20241105

Claims (20)

1 . A package structure, comprising: a circuit substrate; a semiconductor package disposed on and electrically connected to the circuit substrate, wherein the semiconductor package comprises: an interconnection structure; a plurality of first passive devices electrically connected to the interconnection structure, and arranged as a first pattern in between the interconnection structure and the circuit substrate; a plurality of second passive devices electrically connected to the interconnection structure, and arranged as a second pattern in between the interconnection structure and the circuit substrate, wherein the second pattern is different from the first pattern; and a plurality of bump structures electrically connecting the interconnection structure to the circuit substrate and laterally surrounding the plurality of first passive devices and the plurality of second passive devices.
2 . The package structure according to claim 1 , wherein the plurality of first passive devices is arranged as an orthogonal grid pattern in between the interconnection structure and the circuit substrate.
3 . The package structure according to claim 1 , wherein the plurality of second passive devices is arranged as a staggered pattern in between the interconnection structure and the circuit substrate.
4 . The package structure according to claim 3 , wherein a ratio of a number of the plurality of second passive devices relative to a total number of the plurality of first passive devices and the plurality of second passive devices is in a range of 1% to 60%.
5 . The package structure according to claim 1 , wherein the plurality of second passive devices is arranged to have a tilted pattern, whereby sidewalls of the plurality of second passive devices are tilted at an angle relative to a sidewall of the interconnection structure, and the angle is not 90°.
6 . The package structure according to claim 1 , wherein the plurality of second passive devices arranged as the second pattern are arranged in a plurality of columns and a plurality of rows, wherein sidewalls of the plurality of second passive devices arranged in one column of the plurality of columns is misaligned with sidewalls of the plurality of second passive devices arranged in a subsequent column of the plurality of columns.
7 . The package structure according to claim 1 , further comprising an underfill structure covering and contacting the plurality of first passive devices, the plurality of second passive devices and the plurality of bump structures.
8 . A package structure, comprising: an interconnection structure, comprising a first surface and a second surface opposite to the first surface, wherein the second surface includes a first bonding region; a semiconductor die disposed on the first surface of the interconnection structure overlapped with the first bonding region, and electrically connected to the interconnection structure, wherein the semiconductor die includes first sidewalls extending along a first direction, and second sidewalls extending along a second direction perpendicular to the first direction; a plurality of bump structures disposed on the second surface of the interconnection structure in the first bonding region, and electrically connected to the interconnection structure, wherein the first bonding region includes a plurality of first bump-free zones and a plurality of second bump-free zones that are free of the plurality of bump structures, the plurality of first bump-free zones is separated from one another and arranged as an orthogonal grid pattern, and each of the plurality of the first bump-free zones include first zone boundaries that are arranged in parallel with and extending along the first direction, and second zone boundaries that are arranged in parallel with and extending along the second direction, and the plurality of second bump-free zones is separated from one another and arranged in a different manner with the plurality of first bump-free zones; a plurality of passive devices disposed in the plurality of first bump-free zones and the plurality of second bump-free zones.
9 . The package structure according to claim 8 , wherein from a top view of the first bonding region at the second surface of the interconnection structure, an area occupied by each of the plurality of first bump-free zones is greater than an area occupied by each of the plurality of passive devices, and an area occupied by each of the plurality of second bump-free zones is greater than the area occupied by each of the plurality of passive devices.
10 . The package structure according to claim 8 , wherein the plurality of first bump-free zones is separated from one another by a first spacing, the plurality of second bump-free zones is separated from one another by a second spacing, and the plurality of bump structures is disposed in the first bonding region with a third spacing, wherein the first spacing and the second spacing are greater than the third spacing.
11 . The package structure according to claim 8 , wherein the plurality of second bump-free zones is arranged as a staggered pattern.
12 . The package structure according to claim 8 , wherein each of the plurality of second bump-free zones include third zone boundaries that are arranged in parallel with and extending along a third direction, and fourth zone boundaries that are arranged in parallel with and extending along a fourth direction perpendicular to the third direction, wherein the third direction and the fourth direction are different from the first direction and the second direction.
13 . The package structure according to claim 8 , wherein the first bonding region includes a center region and side regions located on two sides of the center region, and wherein the plurality of second bump-free zones is located in the center region, and the plurality of first bump-free zones is located in the side regions.
14 . The package structure according to claim 8 , wherein the second surface of the interconnection structure further comprises a plurality of second bonding regions, and the plurality of bump structures is further disposed on the second surface of the interconnection structure in the plurality of second bonding regions, and the plurality of second bonding regions is free of passive devices, and wherein the package structure further comprises a plurality of second semiconductor dies disposed on the first surface of the interconnection structure and overlapped with the plurality of second bonding regions.
15 . The package structure according to claim 8 , wherein the plurality of passive devices includes a plurality of first passive devices disposed in the plurality of first bump-free zones, and a plurality of second passive devices disposed in the plurality of second bump-free zones, wherein first sidewalls of the plurality of first passive devices are arranged to be in parallel with the first zone boundaries, second sidewalls of the plurality of first passive devices are arranged to be in parallel with the second zone boundaries, and wherein sidewalls of the plurality of second passive devices are arranged to be in parallel with zone boundaries of the plurality of second bump-free zones.
16 . A method of fabricating a package structure, comprising: forming a semiconductor package, which comprises: forming an interconnection structure; electrically connecting a plurality of first passive devices to the interconnection structure, wherein the plurality of first passive devices is arranged as a first pattern on the interconnection structure; electrically connecting a plurality of second passive devices to the interconnection structure, wherein the plurality of second passive devices is arranged as a second pattern on the interconnection structure, and the second pattern is different from the first pattern; and electrically connecting a plurality of bump structures to the interconnection structure, wherein the plurality of bump structures is laterally surrounding the plurality of first passive devices and the plurality of second passive devices; bonding the semiconductor package to a circuit substrate, so that the semiconductor package is electrically connected to the circuit substrate, and wherein the plurality of first passive devices and the plurality of second passive devices are located in between the interconnection structure and the circuit substrate, and the plurality of bump structures is electrically connecting the interconnection structure to the circuit substrate.
17 . The method according to claim 16 , wherein the plurality of first passive devices is arranged as an orthogonal grid pattern on the interconnection structure.
18 . The method according to claim 16 , wherein the plurality of second passive devices is arranged as a staggered pattern on the interconnection structure.
19 . The method according to claim 16 , wherein forming the semiconductor package further comprises bonding a plurality of semiconductor dies to a first surface of the interconnection structure, wherein the first surface is opposite to a second surface of the interconnection structure where the plurality of first passive devices and the plurality of second passive devices are located.
20 . The method according to claim 16 , wherein after bonding the semiconductor package to a circuit substrate, the method further comprises forming an underfill structure covering and contacting the plurality of first passive devices, the plurality of second passive devices and the plurality of bump structures.

Description

BACKGROUND The semiconductor industry has experienced rapid growth due to ongoing improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, improvement in integration density has resulted from iterative reduction of minimum feature size, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices has grown, a need for smaller and more creative packaging techniques of semiconductor dies has emerged. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 to FIG. 12 are schematic sectional and top views of various stages in a method of fabricating a package structure according to some exemplary embodiments of the present disclosure. FIG. 13 is a schematic top view from a second surface of an interconnection structure in a package structure according to some exemplary embodiments of the present disclosure. FIG. 14 is a schematic top view from a second surface of an interconnection structure in a package structure according to some other exemplary embodiments of the present disclosure. FIG. 15 is a schematic top view from a second surface of an interconnection structure in a package structure according to some other exemplary embodiments of the present disclosure. FIG. 16 is a schematic sectional view of a package structure according to some other exemplary embodiments of the present disclosure. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, or the like, are described below to simplify the disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, or the like, are contemplated. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. During the fabrication of package structures, an underfill structure is generally formed in between a circuit substrate and an interconnection structure of a semiconductor package to protect and surround bump structures and integrated passive devices (IPDs). Due to the orthogonal grid-like pattern arrangement (or parallel arrangement) of the IPDs on the interconnection structure, there is a high risk of forming voids during the filling of an underfill material to surround the IPDs and the bump structures. For example, when the underfill material if filled into a bump-free zone of the IPDs, the different capillary pressure between the bump-free zone of the IPDs and the surrounding bump structures will cause the underfill flow rate to be highly different, resulting in the formation of voids or air traps. In accordance with some embodiments of the present disclosure, a package structure is formed so that a risk of underfill voids or formation of air traps can be reduced, and the yield and reliability of the package are enhanced. FIG. 1 to FIG. 12 are schematic sectional and top views of various stages in a method of fabricating a package structure according to some exemplary embodiments of the present disclosure. Referring to FIG. 1, a carrier 102 is provided. In some embodiments, the carrier 102 may be a glass carrier or any suitable carrier for carrying a semiconductor wafer or a reconstituted wafer for the manufacturing method of the p