US-20260130282-A1 - HIGH BANDWIDTH BONDED ASSEMBLY WITH THROUGH-SUBSTRATE VIA STRUCTURES SHIELDED BY GUARD RINGS AND METHODS FOR FORMING THE SAME

US20260130282A1US 20260130282 A1US20260130282 A1US 20260130282A1US-20260130282-A1

Abstract

A semiconductor structure includes a first unit bonded assembly including a first memory die bonded to a first logic die by direct copper to copper bonding, where that the first logic die includes first through-substrate via structures laterally surrounded by first doped semiconductor well guard rings, and a second unit bonded assembly including a second memory die bonded to a second logic die by direct copper to copper bonding. The first unit bonded assembly is bonded to a second unit bonded assembly by solder balls.

Inventors

Guangyuan LI
Mark KRAMAN
Fumiaki TOYAMA

Assignees

SanDisk Technologies, Inc.

Dates

Publication Date: 20260507
Application Date: 20241107

Claims (20)

1 . A semiconductor structure comprising a vertically bonded stack of multiple unit bonded assemblies that are stacked along a vertical direction, wherein each unit bonded assembly of the multiple unit bonded assemblies comprises: a memory die including an alternating stack of insulating layers and electrically conductive layers, memory stack structures vertically extending through the alternating stack, a set of memory-die metal interconnect structures embedded within a set of memory-die dielectric material layers, memory-die intra-assembly bonding pads, and memory-die inter-assembly bonding pads; and a logic die including a controller circuit configured to control operation of the memory stack structures in the memory die, a set of logic-die metal interconnect structures embedded within a set of logic-die dielectric material layers, logic-die intra-assembly bonding pads that are bonded to the memory-die intra-assembly bonding pads, logic-die inter-assembly bonding pads, a logic-die substrate on which the controller circuit is located, through-substrate via structures that vertically extend at least through the logic-die substrate, and a doped semiconductor well laterally surrounding at least one of the through-substrate via structures.
2 . The semiconductor structure of claim 1 , wherein each of the through-substrate via structures is surrounded one of a plurality of doped semiconductor wells.
3 . The semiconductor structure of claim 2 , wherein the plurality of doped semiconductor wells comprise guard rings.
4 . The semiconductor structure of claim 3 , wherein: the logic-die substrate comprises a doped substrate semiconductor layer; the doped semiconductor well has a doping type that is opposite of a doping type of the doped substrate semiconductor layer; and a p-n junction is present at an interface between the substrate semiconductor layer and the doped semiconductor well.
5 . The semiconductor structure of claim 4 , wherein the doped semiconductor well is laterally spaced from said one of the through-substrate via structures by a combination of a dielectric spacer that laterally surrounds said one of the through-substrate via structures and a portion of the substrate semiconductor layer.
6 . The semiconductor structure of claim 5 , wherein the p-n junction is not in direct contact with the dielectric spacer.
7 . The semiconductor structure of claim 4 , wherein: the logic die within each unit bonded assembly further comprises a shallow trench isolation structure located on a top portion of the substrate semiconductor layer and laterally surrounding said one of the through-substrate via structures; an inner sidewall of the doped semiconductor well is in contact with a sidewall of the shallow trench isolation structure; and a bottom surface of the doped semiconductor well is vertically spaced from a backside surface of the substrate semiconductor layer.
8 . The semiconductor structure of claim 4 , wherein: the substrate semiconductor layer includes electrical dopants of a first conductivity type at a first atomic concentration in a range from 1.0×10 13 /cm 3 to 3.0×10 17 /cm 3 ; and the doped semiconductor well includes electrical dopants of a second conductivity type which is opposite of the first conductivity type at a second atomic concentration in a range from 1.0×10 19 /cm 3 to 2.0×10 21 /cm 3 .
9 . The semiconductor structure of claim 1 , wherein the doped semiconductor well is electrically connected to electrical ground of the logic die.
10 . The semiconductor structure of claim 1 , wherein: each vertically neighboring pair of unit bonded assemblies within the vertically bonded stack is bonded to each other by solder balls; and the logic-die intra-assembly bonding pads are bonded to the memory-die intra-assembly bonding pads by direct copper to copper bonding within each unit bonded assembly.
11 . The semiconductor structure of claim 10 , wherein a memory-die dielectric material layer within the set of memory-die dielectric material layers is bonded to a logic-die dielectric material layer within the set of logic-die dielectric material layers by dielectric-to-dielectric bonding.
12 . The semiconductor structure of claim 1 , wherein the memory die further comprises: a source layer in contact with end portions of vertical semiconductor channels within the memory stack structures; and at least one source connection structure in contact with a backside surface of the source layer, wherein a subset of the memory-die inter-assembly bonding pads is electrically connected to the at least one source connection structure.
13 . The semiconductor structure of claim 1 , wherein: the memory die does not include a semiconductor substrate nor through-substrate via structures; and the memory stack structures each comprise a vertical semiconductor channel and a memory film.
14 . A semiconductor structure, comprising: a first unit bonded assembly comprising a first memory die bonded to a first logic die by direct copper to copper bonding, wherein the first logic die comprises first through-substrate via structures laterally surrounded by first doped semiconductor well guard rings; and a second unit bonded assembly comprising a second memory die bonded to a second logic die by direct copper to copper bonding, wherein the first unit bonded assembly is bonded to a second unit bonded assembly by solder balls.
15 . The semiconductor structure of claim 14 , wherein: the first doped semiconductor well guard rings are electrically connected to electrical ground of the first logic die; the second logic die comprises second through-substrate via structures laterally surrounded by second doped semiconductor well guard rings that are electrically connected to electrical ground of the second logic die; the first memory die does not include a semiconductor substrate nor through-substrate via structures; and the second memory die does not include a semiconductor substrate nor through-substrate via structures.
16 . A method of forming a semiconductor structure, comprising: bonding a first memory die to a first logic die by direct copper to copper bonding to form a first unit bonded assembly, wherein the first logic die comprises first through-substrate via structures laterally surrounded by first doped semiconductor well guard rings; bonding a second memory die to a second logic die by direct copper to copper bonding to form a second unit bonded assembly; and bonding the first unit bonded assembly to a second unit bonded assembly by solder balls.
17 . The method of claim 16 , wherein: each of the first memory die and the second memory die comprises an alternating stack of insulating layers and electrically conductive layers, memory stack structures vertically extending through the alternating stack, a set of memory-die metal interconnect structures embedded within a set of memory-die dielectric material layers, memory-die intra-assembly bonding pads, and memory-die inter-assembly bonding pads; and each of the first logic die and the second logic die comprises a controller circuit configured to control operation of the memory stack structures in a respective one of the first memory die and the second memory die, a set of logic-die metal interconnect structures embedded within a set of logic-die dielectric material layers, logic-die intra-assembly bonding pads that are bonded to the memory-die intra-assembly bonding pads, and logic-die inter-assembly bonding pads.
18 . The method of claim 16 , wherein: the first memory die is located on a first memory wafer including the first memory die and additional first memory dies; the first logic die is located on a first logic wafer including the first logic die and additional logic dies; the second memory die is located on a second memory wafer including the second memory die and additional second memory dies; and the second logic die is located on a second logic wafer including the second logic die and additional logic dies.
19 . The method of claim 18 , further comprising, prior to bonding the first unit bonded assembly to a second unit bonded assembly by solder balls: bonding the first memory wafer to the first log wafer by copper to copper bonding between respective copper bonding pads; dicing the bonded first memory wafer and the first logic wafer to form the first unit bonded assembly; bonding the second memory wafer to the second logic wafer by copper to copper bonding between respective copper bonding pads; and dicing the bonded second memory wafer and the second logic wafer to form the second unit bonded assembly.
20 . The method of claim 16 , wherein: the first doped semiconductor well guard rings are electrically connected to electrical ground of the first logic die; the second logic die comprises second through-substrate via structures laterally surrounded by second doped semiconductor well guard rings that are electrically connected to electrical ground of the second logic die; the first memory die does not include a semiconductor substrate nor through-substrate via structures; and the second memory die does not include a semiconductor substrate nor through-substrate via structures.

Description

FIELD The present disclosure relates generally to the field of semiconductor devices, and particularly to a high bandwidth bonded assembly with through-substrate via structures shielded by guard rings and methods for forming the same. BACKGROUND Flash memory devices include NAND and NOR memory devices. Such memory devices may be formed by sequentially depositing memory device layers over a driver circuit located on a silicon wafer. SUMMARY According to an aspect of the present disclosure, a semiconductor structure comprises a vertically bonded stack of multiple unit bonded assemblies that are stacked along a vertical direction. Each unit bonded assembly of the multiple unit bonded assemblies comprises: a memory die including an alternating stack of insulating layers and electrically conductive layers, memory stack structures vertically extending through the alternating stack, a set of memory-die metal interconnect structures embedded within a set of memory-die dielectric material layers, memory-die intra-assembly bonding pads, and memory-die inter-assembly bonding pads; and a logic die including a controller circuit configured to control operation of the memory stack structures in the memory die, a set of logic-die metal interconnect structures embedded within a set of logic-die dielectric material layers, logic-die intra-assembly bonding pads that are bonded to the memory-die intra-assembly bonding pads, logic-die inter-assembly bonding pads, a logic-die substrate on which the controller circuit is located, through-substrate via structures that vertically extend at least through the logic-die substrate, and a doped semiconductor well laterally surrounding at least one of the through-substrate via structures. According to another aspect of the present disclosure, a semiconductor structure includes a first unit bonded assembly including a first memory die bonded to a first logic die by direct copper to copper bonding, where that the first logic die includes first through-substrate via structures laterally surrounded by first doped semiconductor well guard rings, and a second unit bonded assembly including a second memory die bonded to a second logic die by direct copper to copper bonding. The first unit bonded assembly is bonded to a second unit bonded assembly by solder balls. According to another aspect of the present disclosure, a method of forming a semiconductor structure includes bonding a first memory die to a first logic die by direct copper to copper bonding to form a first unit bonded assembly, wherein the first logic die comprises first through-substrate via structures laterally surrounded by first doped semiconductor well guard rings; bonding a second memory die to a second logic die by direct copper to copper bonding to form a second unit bonded assembly; and bonding the first unit bonded assembly to a second unit bonded assembly by solder balls. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic vertical cross-sectional view of a region of an exemplary memory die after formation of a backside dielectric layer, in-process source-level material layers, an alternating stack of insulating layers and sacrificial material layers having stepped surfaces, and a retro-stepped dielectric material portion over a carrier wafer according to an embodiment of the present disclosure. FIG. 2A is a schematic vertical cross-sectional view of a region of the exemplary memory die after forming memory openings according to an embodiment of the present disclosure. FIG. 2B is a top-down view of the exemplary memory die of FIG. 2A. The vertical plane A-A′ is the cut plane of the vertical cross-sectional view of FIG. 2A. FIG. 2C is a top-down view of the exemplary memory die at the processing steps of FIGS. 2A and 2B. FIGS. 3A-3D are sequential vertical cross-sectional views of a memory opening during formation of a memory opening fill structure according to an embodiment of the present disclosure. FIG. 4 is a vertical cross-sectional view of a region of the exemplary memory die after formation of memory opening fill structures according to an embodiment of the present disclosure. FIG. 5A is a vertical cross-sectional view of a region of the exemplary memory die after formation of a contact-level dielectric layer, a patterned hard mask layer, lateral isolation trenches, and discrete through-stack openings according to an embodiment of the present disclosure. FIG. 5B is a top-down view of a region of the exemplary memory die of FIG. 5A. The vertical plane A-A′ is the cut plane of the vertical cross-sectional view of FIG. 5A. FIG. 5C is a top-down view of the exemplary memory die at the processing steps of FIGS. 5A and 5B. FIG. 6 is a vertical cross-sectional view of a region of the exemplary memory die after vertical extension of the discrete through-stack openings according to an embodiment of the present disclosure. FIG. 7 is a vertical cross-sectional view of a region of the exemplary memory die after formation o