US-20260130284-A1 - SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME

Abstract

A semiconductor package includes a base chip, a first semiconductor chip group including a plurality of first semiconductor chips stacked on the base chip in a vertical direction, a second semiconductor chip group including a plurality of second semiconductor chips stacked on the first semiconductor chip group in the vertical direction, a plurality of first connection bumps on lower surfaces of the plurality of first semiconductor chips, a plurality of second connection bumps on lower surfaces of the plurality of second semiconductor chips, a first adhesive layer surrounding the plurality of first connection bumps and the first semiconductor chip group, and a second adhesive layer surrounding the plurality of second connection bumps and the second semiconductor chip group.

Inventors

• Hanmin Lee
• Sangsick Park

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260507

Application Date

20250903

Priority Date

20241106

Claims (20)

1. 1 . A semiconductor package comprising: a base chip; a first semiconductor chip group comprising a plurality of first semiconductor chips stacked on the base chip in a vertical direction; a second semiconductor chip group comprising a plurality of second semiconductor chips stacked on the first semiconductor chip group in the vertical direction; a plurality of first connection bumps on lower surfaces of the plurality of first semiconductor chips; a plurality of second connection bumps on lower surfaces of the plurality of second semiconductor chips; a first adhesive layer surrounding the plurality of first connection bumps and the first semiconductor chip group; and a second adhesive layer surrounding the plurality of second connection bumps and the second semiconductor chip group.
2. 2 . The semiconductor package of claim 1 , wherein the plurality of first semiconductor chips comprise a first semiconductor chip and a second semiconductor chip stacked in the vertical direction, wherein the first adhesive layer comprises a single body covering a lower surface and side surfaces of the first semiconductor chip and a lower surface and side surfaces of the second semiconductor chip, wherein the plurality of second semiconductor chips comprise a third semiconductor chip and a fourth semiconductor chip stacked in the vertical direction, and wherein the second adhesive layer comprises a single body covering a lower surface and side surfaces of the third semiconductor chip and a lower surface and side surfaces of the fourth semiconductor chip.
3. 3 . The semiconductor package of claim 1 , wherein the first adhesive layer comprises a plurality of first horizontal portions covering each lower surface of the plurality of first semiconductor chips and a first vertical portion covering each side surface of the plurality of first semiconductor chips, and wherein the second adhesive layer comprises a plurality of second horizontal portions covering each lower surface of the plurality of second semiconductor chips and a second vertical portion covering each side surface of the plurality of second semiconductor chips.
4. 4 . The semiconductor package of claim 3 , wherein the first vertical portion comprises a first surface connected to each of the plurality of first horizontal portions, and a second surface that is opposite to the first surface and that is curved, and wherein the second vertical portion comprises a third surface connected to each of the plurality of second horizontal portions, and a fourth surface that is opposite to the third surface and that is curved.
5. 5 . The semiconductor package of claim 4 , wherein a horizontal width of the first vertical portion increases and then decreases in the vertical direction from a bottom surface of the first adhesive layer, and wherein a horizontal width of the second vertical portion increases and then decreases in the vertical direction from a bottom surface of the second adhesive layer.
6. 6 . The semiconductor package of claim 1 , wherein each of the plurality of first semiconductor chips and the plurality of second semiconductor chips comprises: a semiconductor substrate comprising through electrodes; a front structure covering a lower surface of the semiconductor substrate and comprising a plurality of devices; a passivation layer covering an upper surface of the semiconductor substrate; and a plurality of pads connected to the through electrodes.
7. 7 . The semiconductor package of claim 1 , wherein a number of the plurality of first semiconductor chips is different from a number of the plurality of second semiconductor chips.
8. 8 . A semiconductor package comprising: a base chip; a first semiconductor chip and a second semiconductor chip stacked on the base chip in a vertical direction; a plurality of first connection bumps between the base chip and the first semiconductor chip, and between the first semiconductor chip and the second semiconductor chip; a first adhesive layer surrounding the plurality of first connection bumps; and an encapsulation layer covering an upper surface of the base chip, the first semiconductor chip, the second semiconductor chip, and the first adhesive layer, wherein the first adhesive layer comprises a single body covering a lower surface and side surfaces of the first semiconductor chip and a lower surface and side surfaces of the second semiconductor chip.
9. 9 . The semiconductor package of claim 8 , further comprising: a third semiconductor chip stacked on the second semiconductor chip in the vertical direction, wherein the first adhesive layer further covers a lower surface and side surfaces of the third semiconductor chip.
10. 10 . The semiconductor package of claim 8 , wherein the first adhesive layer comprises: a first horizontal portion between the base chip and the first semiconductor chip; a second horizontal portion between the first semiconductor chip and the second semiconductor chip; and a first vertical portion covering side surfaces of the first semiconductor chip and side surfaces of the second semiconductor chip, and wherein the first horizontal portion, the second horizontal portion, and the first vertical portion comprise a single body.
11. 11 . The semiconductor package of claim 10 , wherein a first surface of the first vertical portion is connected to the first horizontal portion and the second horizontal portion, and a second surface of the first vertical portion that is opposite to the first is curved.
12. 12 . The semiconductor package of claim 11 , wherein a horizontal width of the first vertical portion increases and then decreases in the vertical direction from a bottom surface of the first adhesive layer.
13. 13 . The semiconductor package of claim 12 , wherein a horizontal width of the first vertical portion is largest in a center of the first vertical portion in the vertical direction.
14. 14 . The semiconductor package of claim 8 , further comprising: a third semiconductor chip and a fourth semiconductor chip stacked on the second semiconductor chip in the vertical direction; a plurality of second connection bumps between the second semiconductor chip and the third semiconductor chip, and between the third semiconductor chip and the fourth semiconductor chip; and a second adhesive layer comprising a single body covering a lower surface and side surfaces of the third semiconductor chip and a lower surface and side surfaces of the fourth semiconductor chip.
15. 15 . The semiconductor package of claim 14 , wherein the second adhesive layer comprises: a third horizontal portion between the second semiconductor chip and the third semiconductor chip; a fourth horizontal portion between the third semiconductor chip and the fourth semiconductor chip; and a second vertical portion covering side surfaces of the third semiconductor chip and side surfaces of the fourth semiconductor chip, and wherein the third horizontal portion, the fourth horizontal portion, and the second vertical portion comprise a single body.
16. 16 . The semiconductor package of claim 14 , wherein the encapsulation layer covers the third semiconductor chip, the fourth semiconductor chip, and the second adhesive layer.
17. 17 . A method of fabricating a semiconductor package, the method comprising: preparing a base chip; providing a first semiconductor chip on the base chip in a vertical direction; providing a second semiconductor chip on the first semiconductor chip in the vertical direction; and thermally compressing the first semiconductor chip and the second semiconductor chip onto the base chip by performing first thermal compression, wherein the performing of the first thermal compression comprises forming a first adhesive layer as a single body covering a lower surface and side surfaces of the first semiconductor chip, and a lower surface and side surfaces of the second semiconductor chip.
18. 18 . The method of claim 17 , further comprising: providing a third semiconductor chip on the second semiconductor chip in the vertical direction; providing a fourth semiconductor chip on the third semiconductor chip in the vertical direction; and thermally compressing the third semiconductor chip and the fourth semiconductor chip onto the second semiconductor chip by performing second thermal compression, wherein the performing of the second thermal compression comprises forming a second adhesive layer as a single body covering a lower surface and side surfaces of the third semiconductor chip, and a lower surface and side surfaces of the fourth semiconductor chip.
19. 19 . The method of claim 17 , wherein the performing of the first thermal compression further comprises simultaneously adhering a plurality of connection bumps arranged between the base chip and the first semiconductor chip and between the first semiconductor chip and the second semiconductor chip.
20. 20 . The method of claim 17 , further comprising providing a third semiconductor chip on the second semiconductor chip in the vertical direction, wherein the performing of the first thermal compression further comprises forming the first adhesive layer as a single body covering a lower surface and side surfaces of the first semiconductor chip, a lower surface and side surfaces of the second semiconductor chip, and a lower surface and side surfaces of the third semiconductor chip.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2024-0156464, filed on Nov. 6, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety. BACKGROUND The present disclosure relates to a semiconductor package and a method of fabricating the semiconductor package, and more particularly, to a semiconductor package in which a plurality of semiconductor chips are stacked, and a method of fabricating the semiconductor package. Recently, the demand for portable devices has been rapidly increasing in the electronic product market, and this has led to continuous demands for miniaturization and weight reduction of electronic components mounted on these electronic products. In order to miniaturize and lighten electronic components, semiconductor packages mounted on the electronic components are required to be smaller in size while also being able to process large amounts of data. As these semiconductor packages become more highly integrated, improvements in reliability and processability of the semiconductor packages are required. Information disclosed in this Background section has already been known to or derived by the inventors before or during the process of achieving the embodiments of the present application, or is technical information acquired in the process of achieving the embodiments. Therefore, it may contain information that does not form the prior art that is already known to the public. SUMMARY One or more example embodiments provide a semiconductor package with enhanced reliability, and a method of fabricating the semiconductor package. Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments. According to an aspect of an example embodiment, a semiconductor package may include a base chip, a first semiconductor chip group including a plurality of first semiconductor chips stacked on the base chip in a vertical direction, a second semiconductor chip group including a plurality of second semiconductor chips stacked on the first semiconductor chip group in the vertical direction, a plurality of first connection bumps on lower surfaces of the plurality of first semiconductor chips, a plurality of second connection bumps on lower surfaces of the plurality of second semiconductor chips, a first adhesive layer surrounding the plurality of first connection bumps and the first semiconductor chip group, and a second adhesive layer surrounding the plurality of second connection bumps and the second semiconductor chip group. According to an aspect of an example embodiment, a semiconductor package may include a base chip, a first semiconductor chip and a second semiconductor chip stacked on the base chip in a vertical direction, a plurality of first connection bumps between the base chip and the first semiconductor chip, and between the first semiconductor chip and the second semiconductor chip, a first adhesive layer surrounding the plurality of first connection bumps, and an encapsulation layer covering an upper surface of the base chip, the first semiconductor chip, the second semiconductor chip, and the first adhesive layer, where the first adhesive layer includes a single body covering a lower surface and side surfaces of the first semiconductor chip and a lower surface and side surfaces of the second semiconductor chip. According to an aspect of an example embodiment, a method of fabricating a semiconductor package may include preparing a base chip, providing a first semiconductor chip on the base chip in a vertical direction, providing a second semiconductor chip on the first semiconductor chip in the vertical direction, and thermally compressing the first semiconductor chip and the second semiconductor chip onto the base chip by performing first thermal compression, where the performing of the first thermal compression includes forming a first adhesive layer as a single body covering a lower surface and side surfaces of the first semiconductor chip, and a lower surface and side surfaces of the second semiconductor chip. BRIEF DESCRIPTION OF THE DRAWINGS The above and other aspects, features, and advantages of certain example embodiments of the present disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which: FIG. 1 is a cross-sectional view illustrating a configuration of a semiconductor package according to one or more embodiments; FIG. 2 is an enlarged cross-sectional view of portion “EX1” of FIG. 1 according to one or more embodiments; FIG. 3 is a graph showing a horizontal length of a vertical portion of an adhesive layer of a semiconductor package according to one or more embodiments; FIG. 4 is a cross-sectional view illustrating a configura