US-20260130285-A1 - SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME

Abstract

The semiconductor device may include a substrate, a first insulating layer on a bottom surface of the substrate, an interconnection structure in the first insulating layer, a second insulating layer on a bottom surface of the first insulating layer, and a plurality of lower pads provided in the second insulating layer. Each lower pad may be provided such that a width of a top surface thereof is smaller than a width of a bottom surface thereof. The lower pads may include first, second, and third lower pads. In a plan view, the first and third lower pads may be adjacent to center and edge portions of the substrate, respectively, and the second lower pad may be disposed therebetween. A width of a bottom surface of the second lower pad may be smaller than that of the first lower pad and may be larger than that of the third lower pad.

Inventors

• Jun Young Oh
• Un-Byoung Kang
• Byeongchan KIM
• Jumyong Park
• Chungsun Lee

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260507

Application Date

20251219

Priority Date

20211022

Claims (20)

1. 1 . A semiconductor package comprising: a lower semiconductor chip; and an upper semiconductor chip on the lower semiconductor chip, wherein each of the lower semiconductor chip and the upper semiconductor chip comprises: a substrate; a first insulating layer on a bottom surface of the substrate; and an interconnection structure provided in the first insulating layer, wherein the lower semiconductor chip further comprises penetration vias penetrating the substrate, wherein the penetration vias comprise a first via, a second via, and a third via, wherein the first via is adjacent to a center of the substrate, the third via is adjacent to an edge of the substrate, and the second via is between the first via and the third via, when viewed in a plan view, wherein a width of the first via is greater than a width of the second via, and wherein the width of the second via is greater than a width of the third via.
2. 2 . The semiconductor package of claim 1 , wherein each of the interconnection structures comprises conductive vias, which are provided to penetrate a portion of the first insulating layer, and conductive patterns, which are electrically connected to the conductive vias, and wherein the penetration vias of the lower semiconductor chip are in contact with lowermost ones of the conductive vias of the upper semiconductor chip.
3. 3 . The semiconductor package of claim 1 , wherein as a distance to the center of the substrate decreases, widths of the penetration vias gradually increase, when viewed in the plan view.
4. 4 . A semiconductor package comprising: a substrate; a first insulating layer on a bottom surface of the substrate; interconnection structures provided in the first insulating layer; a second insulating layer on a bottom surface of the first insulating layer; a plurality of lower pads provided in the second insulating layer; and penetration vias penetrating the substrate, wherein top surfaces of the plurality of lower pads are coplanar with a top surface of the second insulating layer, and bottom surfaces of the plurality of lower pads are coplanar with a bottom surface of the second insulating layer, wherein the penetration vias comprise a first via adjacent to a center of the substrate and a second via adjacent to an edge of the substrate, when viewed in a plan view, wherein a width of the first via is greater than a width of the second via, wherein the plurality of lower pads comprises a first lower pad, a second lower pad, and a third lower pad, wherein the first lower pad is adjacent to the center of the substrate, the third lower pad is adjacent to the edge of the substrate, and the second lower pad is between the first lower pad and the third lower pad, when viewed in the plan view, wherein a width of the bottom surface of the first lower pad is greater than a width of the bottom surface of the second lower pad, wherein the width of the bottom surface of the second lower pad is greater than a width of the bottom surface of the third lower pad, wherein a width of each of the plurality of lower pads gradually increases from the top surface toward the bottom surface thereof, and wherein the bottom surface of each of the plurality of lower pads directly contacts a top surface of a corresponding upper pad of an adjacent semiconductor chip.
5. 5 . The semiconductor package of claim 4 , wherein, in a cross-sectional view, each of the plurality of lower pads has one of a triangular shape and a trapezoidal shape.
6. 6 . The semiconductor package of claim 4 , wherein each of the plurality of lower pads has one of a circular shape, a triangular shape, a quadrangular shape, and a polygonal shape having five or more sides, when viewed in the plan view.
7. 7 . The semiconductor package of claim 4 , wherein widths of the bottom surfaces of the plurality of lower pads gradually increase toward the center of the substrate, when viewed in the plan view, wherein the width of the bottom surface of the first lower pad is from 110% to 150% of the width of the bottom surface of the second lower pad, and wherein the width of the bottom surface of the first lower pad is greater than 150% and less than or equal to 500% of the width of the bottom surface of the third lower pad.
8. 8 . The semiconductor package of claim 4 , further comprising: a third insulating layer on a top surface of the substrate; and a plurality of upper pads provided in the third insulating layer, wherein each of the plurality of upper pads has a top surface having a width greater than a width of a bottom surface thereof.
9. 9 . The semiconductor package of claim 8 , wherein the plurality of upper pads comprises a first upper pad, a second upper pad, and a third upper pad, wherein the first upper pad is adjacent to the center of the substrate, the third upper pad is adjacent to the edge of the substrate, and the second upper pad is between the first upper pad and the third upper pad, when viewed in the plan view, wherein the width of the top surface of the first upper pad is greater than the width of the top surface of the second upper pad, and wherein the width of the top surface of the second upper pad is greater than the width of the top surface of the third upper pad.
10. 10 . The semiconductor package of claim 8 , wherein the penetration vias are connected to the interconnection structures, and wherein the plurality of upper pads and the plurality of lower pads are electrically connected by the penetration vias.
11. 11 . The semiconductor package of claim 8 , wherein the bottom surface of each of the plurality of lower pads is flat, and wherein the top surface of each of the plurality of upper pads is flat.
12. 12 . The semiconductor package of claim 8 , wherein, in a cross-sectional view, each of the plurality of upper pads has one of a triangular shape and a trapezoidal shape.
13. 13 . The semiconductor package of claim 8 , wherein each of the plurality of upper pads has one of a circular shape, a triangular shape, a quadrangular shape, and a polygonal shape having five or more sides, when viewed in the plan view.
14. 14 . The semiconductor package of claim 4 , wherein a total area of the plurality of lower pads within a first unit region is greater than a total area of the plurality of lower pads within a second unit region, when viewed in the plan view, wherein an area of the first unit region is equal to an area of the second unit region, and wherein widths of top surfaces of the plurality of lower pads within the first unit region is greater than widths of top surfaces of the plurality of lower pads within the second unit region.
15. 15 . A semiconductor package comprising: a first semiconductor chip; and a second semiconductor chip on the first semiconductor chip, wherein each of the first semiconductor chip and the second semiconductor chip comprises: a substrate; a first insulating layer on a bottom surface of the substrate; interconnection structures provided in the first insulating layer; a second insulating layer on a bottom surface of the first insulating layer; and lower pads provided in the second insulating layer and connected to the interconnection structures, wherein the first semiconductor chip further comprises penetration vias penetrating the substrate, a third insulating layer on the substrate, and upper pads provided in the third insulating layer, wherein the lower pads of the second semiconductor chip are connected to the upper pads of the first semiconductor chip, wherein the penetration vias connect the upper pads of the first semiconductor chip with corresponding interconnection structures of the first semiconductor chip, wherein the penetration vias comprise a first via adjacent to a center of the substrate and a second via adjacent to an edge of the substrate, when viewed in a plan view, and wherein a width of the first via is greater than a width of the second via.
16. 16 . The semiconductor package of claim 15 , wherein each of the interconnection structures comprises conductive vias penetrating a portion of the first insulating layer and conductive patterns electrically connected to the conductive vias, and wherein the penetration vias of the first semiconductor chip contact lowermost ones of the conductive vias of the second semiconductor chip.
17. 17 . The semiconductor package of claim 15 , wherein the third insulating layer directly contacts the second insulating layer of the second semiconductor chip.
18. 18 . The semiconductor package of claim 15 , wherein each of the upper pads has a top surface having a width greater than a width of a bottom surface thereof, and wherein each of the lower pads has a top surface having a width smaller than a width of a bottom surface thereof.
19. 19 . The semiconductor package of claim 15 , further comprising: a package substrate spaced apart from the second semiconductor chip with the first semiconductor chip interposed therebetween; a third semiconductor chip between the package substrate and the first semiconductor chip; and connection terminals between the package substrate and the third semiconductor chip, wherein the third semiconductor chip comprises chip pads adjacent to a top surface thereof, and wherein the chip pads contact the lower pads of the first semiconductor chip.
20. 20 . The semiconductor package of claim 19 , further comprising: a fourth semiconductor chip horizontally spaced apart from the third semiconductor chip, wherein the fourth semiconductor chip comprises a semiconductor chip of a different type from the first semiconductor chip.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This U.S. non-provisional patent application is a continuation of U.S. Application No. Ser. No. 17/870,898, filed Jul. 22, 2022, in the U.S. Patent and Trademark Office, which claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2021-0142112, filed on Oct. 22, 2021, in the Korean Intellectual Property Office, the entire contents of all of which are hereby incorporated by reference. BACKGROUND The present disclosure relates to a semiconductor device and a semiconductor package including the same, and in particular, to a semiconductor device with improved reliability and a semiconductor package including the same. With the recent advance in the electronics industry, demand for high-performance, high-speed, and compact electronic components are increasing. To meet this demand, packaging technologies of mounting a plurality of semiconductor chips in a single package are being developed. Recently, demand for portable electronic devices has been rapidly increasing in the market, and thus, it is necessary to reduce sizes and weights of electronic components constituting the portable electronic devices. For this, it is necessary to develop packaging technologies of reducing a size and a weight of each component and of integrating a plurality of individual components in a single package. In particular, for a semiconductor package used to process high frequency signals, it is necessary not only to reduce a size of a product but also to realize good electrical characteristics. SUMMARY An embodiment of the inventive concept provides a semiconductor device with improved reliability. An embodiment of the inventive concept provides a semiconductor package including a semiconductor device with improved reliability. According to an embodiment of the inventive concept, a semiconductor device may include a substrate, a first insulating layer on a bottom surface of the substrate, an interconnection structure provided in the first insulating layer, a second insulating layer on a bottom surface of the first insulating layer, and a plurality of lower pads provided in the second insulating layer. Each of the lower pads may be provided such that a width of a top surface thereof is smaller than a width of a bottom surface thereof. The lower pads may include a first lower pad, a second lower pad, and a third lower pad. When viewed in a plan view, the first lower pad may be adjacent to a center of the substrate, the third lower pad may be adjacent to an edge of the substrate, and the second lower pad may be disposed between the first lower pad and the third lower pad. A width of a bottom surface of the first lower pad may be larger than a width of a bottom surface of the second lower pad, and the width of the bottom surface of the second lower pad may be larger than a width of a bottom surface of the third lower pad. According to an embodiment of the inventive concept, a semiconductor package may include a first semiconductor chip and a second semiconductor chip on a bottom surface of the first semiconductor chip. The first semiconductor chip may include a substrate, a first insulating layer on a bottom surface of the substrate, an interconnection structure provided in the first insulating layer, a second insulating layer on a bottom surface of the first insulating layer, and a plurality of lower pads provided in the second insulating layer. A width of each of the plurality of lower pads may increase as a distance to a bottom surface thereof decreases, and the plurality of lower pads may include a first lower pad adjacent to a center of the substrate and a second lower pad adjacent to an edge of the substrate. A width of a top surface of the first lower pad may be larger than a width of a top surface of the second lower pad. According to an embodiment of the inventive concept, a semiconductor package may include a package substrate, a first lower semiconductor chip on the package substrate, and a first upper semiconductor chip on the first lower semiconductor chip. Each of the first lower and upper semiconductor chips may include a substrate, a first insulating layer on a bottom surface of the substrate, an interconnection structure provided in the first insulating layer, a second insulating layer on a bottom surface of the first insulating layer, and a plurality of lower patterns provided in the second insulating layer. The first lower semiconductor chip may further include a third insulating layer on a top surface of the substrate and a plurality of upper patterns provided in the third insulating layer. The plurality of upper patterns of the first lower semiconductor chip may be in contact with the plurality of lower patterns of the first upper semiconductor chip, and as a distance to a center of the substrate decreases, widths of top surfaces of the plurality of lower patterns may gradually increase, when viewed in a plan view. According to an embodiment of the inventive